Merged array PLA device, circuit, fabrication method and testing technique

Abstract

A merged AND/OR array PLA is disclosed wherein the merger is accomplished by forming the gates of the FET devices in the AND array by means of an upper conductor layer and the gates of the FET devices in the OR array, which are connected to the drain of the devices in the AND array, by means of lower level conductor layer, so that the devices are contiguous. The PLA structure uses a polysilicon layer for interconnection between AND array FET drains and OR array FET gates, with the AND array FETs or OR array FETs being intermixed in a single array. The OR array outputs are oriented vertically, alternating between the AND product terms and ground diffusions. All PLA outputs are oriented vertically within the same array. A testing technique and special testing circuitry is disclosed which makes use of the existing bit partitioning input buffer as the source of test patterns and the existing output latches as the storage for the test response bits for individually testing both the AND components and the OR components in the merged array PLA.

We claim: 
     
       1. A testing circuit for a merged array programmable logic array having an AND array element with an input conductor and product term output conductor which serves as the input to an OR array element having an output conductor, comprising: a first input gating field effect transistor connected between said input conductor and an input signal source having its gate connected through an inverter to a first test bit signal source;   a second input gating field effect transistor connected between said product term conductor and said input signal source having its gate connected to said first test bit signal source;   a first output gating field effect transistor connected between said product term conductor and an output latch and having its gate connected through an inverter to a second test bit signal source;   a second output gating field effect transistor connected between said output conductor and said output latch and having its gate connected to said second test bit signal source;   whereby said AND array field effect transistor device and said OR array field effect transistor device can be independently tested by a simple algorithm of test patterns equivalent in number to the sum of the number of AND array inputs and the number of OR array product terms.   
     
     
       2. In a semiconductor structure for a programmed logic array having an AND array and an OR array of field effect transistor devices, a testing circuit comprising: a semiconductor substrate of a first conductivity type;   a spaced parallel array of diffusion lines of a second conductivity type in said substrate;   a first insulating layer overlying said substrate having a first plurality of openings selectively defining field effect transistor gates for said OR array, second plurality of openings selectively defining field effect transistor drains for said AND array, and a third plurality of openings selectively defining field effect transistor gates in said AND array;   a first, spaced parallel array of conductor lines overlying said first insulator layer and oriented perpendicularly to said diffusion lines, having a conductor passing through one of said first openings to form the gate of a first field effect transistor device in said OR array and passing through one of said third openings proximate to said one of said first openings, to form a drain contact for a second contiguous field effect transistor device in said AND array;   a second insulating layer overlying said first array of conductor lines having a plurality of openings over said second openings in said first insulating layer;   a second spaced, parallel array of conductor lines overlying said second insulator layer and oriented parallel with said first spaced parallel array of conductor lines, having a conductor passing through one of said openings in said second insulating layer to form the gate of said second field effect transistor device, forming an input to said AND array;   a first input gating field effect transistor connected between one of said second conductor lines and an input signal source having its gate connected through an inverter to a first test bit signal source;   a second input gating field effect transistor connected between said one of said first conductor lines and said input signal source having its gate connected to said first test bit signal source;   a first output gating field effect transistor connected between one of said diffusion lines forming the drain of said second field effect transistor AND array device and an output latch and having its gate connected through an inverter to a second test bit signal source;   a second output gating field effect transistor connected between one of said diffusion lines forming the drain of said first field effect transistor OR array device and said output latch and having its gate connected to said second test bit signal source;   whereby said AND array field effect transistor device and said OR array field effect transistor device can be independently tested by a simple algorithm of test patterns equivalent in number to the sum of the number of AND array inputs and the number of OR array product terms.   
     
     
       3. In a semiconductor structure for a programmed logic array having an AND array and an OR array of field effect transistor devices, a testing circuit comprising: a semiconductor substrate of a first conductivity type;   a spaced, parallel array of diffusion segments of a second conductivity type oriented in a first direction;   a first insulating layer lying on said substrate having a first window between first and second ones of said diffusion segments with a relatively thin insulating layer in the bottom thereof forming the gate region for a first field effect transistor device in said AND array, said first insulating layer having a second window between said second one and a third one of said diffusion segments with a relatively thin insulating layer in the bottom thereof forming the gate region for a second field effect transistor device in said OR array;   said first insulating layer having third, fourth and fifth windows over said first, second and third diffusion segments, respectively, as via holes for contacts to a product term conductor, a reference voltage conductor and output conductor, respectively;   a first layer of polycrystalline silicon lying on top of said thin insulating layer in said first window and said thin insulating layer in said second window, serving as the gate electrodes for said first and second field effect transistor devices, respectively;   a second insulating layer lying on top of said first layer of polycrystalline silicon having first and second windows over said first and second field effect transistor devices, respectively and third, fourth and fifth windows over said third, fourth and fifth windows in said first insulating layer;   a second layer of polycrystalline silicon lying on top of said second insulating layer, with a portion passing through said second window in said second insulating layer and contacting said first polycrystalline silicon layer over said second field effect transistor device, forming the said product term conductor line lying in a second direction perpendicular to said first direction with first and second windows over said fourth and fifth windows of said second insulating layer and a via contact to said first diffusion segment, through said third window of said second insulating layer;   a third insulating layer lying on top of said second layer of polycrystalline silicon having a first window over said first window of said second insulating layer and second, third and fourth windows over said third and fourth and fifth windows of said second insulating layer, respectively;   a first layer of metal lying on top of said third insulating layer, forming a plurality of conductor lines oriented in said first direction with a first metal line as a product term conductor lying over said first diffusion segment and connected by means of a via contact through said second window of said third insulating layer to said second layer polycrystalline silicon product term conductor line, with a second metal line as a ground conductor lying over said second diffusion segment and connected by means of a via contact through said third window of said third insulating layer to said second diffusion segment, and with a third metal line as an output conductor lying over said third diffusion segment and connected by means of a via contact through said fourth window of said third insulating layer to said third diffusion segment;   a fourth insulating layer lying on top of said first metal layer, having a window over said first window of said third insulating layer;   a second metal layer lying on top of said fourth insulating layer, forming an input line in said second direction with a portion passing through said window in said fourth insulating layer forming the gate input conductor for said first field effect transistor in said AND array;   a first input gating field effect transistor connected between said input line and an input signal source having its gate connected through an inverter to a first test bit signal source;   a second input gating field effect transistor connected between said product term metal conductor line and said input signal source having its gate connected to said first test bit signal source;   a first output gating field effect transistor connected between said product term metal conductor line and an output latch and having its gate connected through an inverter to a second test bit signal source;   a second output gating field effect transistor connected between said output metal conductor and said output latch and having its gate connected to said second test bit signal source;   whereby said AND array field effect transistor device and said OR array field effect transistor device can be independently tested by a simple algorithm of test patterns equivalent in number to the sum of the number of AND array inputs and the number of OR array product terms.