Complementary latching disabling circuit

Abstract

An oscillator responsive to a control signal generates a first signal at a first rate at an output terminal. A first transistor is coupled to the output terminal and to a load circuit. Normal operation of the load circuit depends upon the first transistor switching conductive states at the first rate. A second complementary type conductivity transistor forms a complementary disabling latch with the first transistor. A fault signal activates the latch and prevents the first transistor from switching conductive states, thereby disabling normal load circuit operation.

What is claimed is: 
     
       1. A disabling circuit comprising: an oscillator circuit with an input terminal responsive to control signals for generating at an output terminal of said oscillator circuit a first signal at a first rate determined by said control signal; a first transistor coupled to said output terminal for switching conductive states at said first rate;   a load circuit coupled to said first transistor, normal operation of said load circuit dependent upon said first transistor switching conductive states at said first rate;   a second transistor of a conductivity type complementary to said first transistor, the appropriate output and input terminals of each of said first and second transistors coupled to one another in a manner forming a complementary latch; and   an input fault terminal coupled to said complementary latch and responsive to a fault signal coupled to said input fault terminal for activating said complementary latch and preventing said first transistor from switching conductive states, thereby disabling normal operation of said load circuit.   
     
     
       2. A circuit according to claim 1, wherein said first transistor comprises a PNP type and said second transistor comprises an NPN type. 
     
     
       3. A circuit according to claim 2, wherein the collector of said first transistor is coupled to the base of said second transistor and the collector of said second transistor is coupled to the base of said first transistor for forming a regenerative path. 
     
     
       4. A circuit according to claim 1, wherein said load circuit comprises a controlled switching device for providing a regulated voltage at a device output terminal, a control terminal of said switching device coupled to said first transistor. 
     
     
       5. A circuit according to claim 4 including a deflection circuit coupled to said controlled switching device, said regulated voltage providing operative power to said deflection circuit. 
     
     
       6. A circuit according to claim 5, wherein said deflection circuit includes an output switching means for generating first and second intervals within a deflection cycle, said fault signal indicative of an excessive current flowing through said output switching means. 
     
     
       7. A circuit according to claim 6, wherein said output switching means comprises a switching transistor, and wherein a current sensing means is coupled to said switching transistor and said fault terminal is coupled to said current sensing means. 
     
     
       8. A circuit according to claim 7, wherein the collector of said first transistor is coupled to the base of said second transistor and the collector of said second transistor is coupled to the base of said first transistor for forming a regenerative path. 
     
     
       9. A circuit according to claim 1, wherein said load circuit comprises a horizontal output stage, said oscillator generating a first signal at a horizontal rate. 
     
     
       10. A circuit according to claim 9, wherein said first transistor is coupled to a horizontal output transistor of said horizontal output stage, activation of said complementary latch disabling said horizontal output transistor. 
     
     
       11. A circuit according to claim 10, wherein the collector of said first transistor is coupled to the base of said second transistor and the collector of said second transistor is coupled to the base of said first transistor for forming a regenerative path. 
     
     
       12. A circuit according to claim 1, including: a source of operative power for said complementary latch coupled to said complementary latch;   biasing means coupled to said source of operative power and a bias terminal of said complementary latch for establishing a threshold level for activating said complementary latch; and   filter means coupled to said input fault terminal for filtering said fault signal, the discharge of said filter means upon the disabling of said source of operative power after the activation of said complementary latch mainly occurring through said bias means providing for deactivating said complementary latch upon the re-enabling of said source of operative power prior to a complete removal of said operative power.   
     
     
       13. A circuit according to claim 12, wherein said filter means is coupled to one of the base and emitter of said second transistor and said biasing means is coupled to the other of said base and emitter. 
     
     
       14. A circuit according to claim 13 including unidirectional conducting means coupled between said input fault terminal and said filter means for preventing said filter means from discharging through said input fault terminal. 
     
     
       15. A circuit according to claim 14, wherein said oscillator includes a third transistor of conductivity type complementary to said first transistor coupled together in a regenerative manner, for maintaining said first and third transistors in identical conductive states when both are switching conductive states at said first rate. 
     
     
       16. A circuit according to claim 15 including capacitive charge-discharge means coupled to said input terminal for establishing said first rate. 
     
     
       17. A disabling circuit comprising: a source of unregulated voltage for supplying energy;   a load circuit;   controllable switching means coupled to said source and said load circuit for transmitting a controlled amount of energy from said source to said load circuit;   controllable oscillator means with an output terminal coupled to a control terminal of said controllable switching means and responsive to a feedback signal representative of an energy level of said load circuit for providing a switching signal at said output terminal to said controllable switching means for regulating said controlled amount of energy, said oscillator including a first transistor changing conductive states at a first rate;   a disabling transistor of a conductivity type complementary to that of said first transistor coupled to said first transistor in a manner forming a complementary latch; and   fault signaling means coupled to an input terminal of said complementary latch and responsive to a fault condition within said load circuit for activating said complementary latch during the occurrence of said fault condition for maintaining said first transistor in a first conductive state when said complementary latch is activated for blocking said switching signal.   
     
     
       18. A circuit according to claim 17, wherein the collector of said first transistor is coupled to the base of said disabling transistor and the collector of said disabling transistor is coupled to the base of said first transistor for forming a regenerative path. 
     
     
       19. A circuit according to claim 17, wherein said load circuit comprises a deflection circuit including output switching means for generating first and second intervals within each deflection cycle. 
     
     
       20. A circuit according to claim 19, wherein said first rate comprises said deflection rate, an inductance in series with said controllable switching means having developed therein a deflection rate voltage, a first polarity of said deflection rate voltage commutating off said controllable switching means. 
     
     
       21. A circuit according to claim 20, wherein said fault signaling means comprises current sensing means coupled to said output switching means for sensing a fault condition wherein an excessive current flows through said output switching means. 
     
     
       22. A circuit according to claim 21, wherein the collector of said first transistor is coupled to the base of said disabling transistor and the collector of said disabling transistor is coupled to the base of said first transistor for forming a regenerative path. 
     
     
       23. A disabling circuit for a deflection circuit comprising: a deflection circuit;   output switching means coupled to said deflection circuit for generating first and second deflection intervals;   a first transistor changing conductive states at a deflection rate in response to deflection rate signals coupled to an input terminal of said first transistor for providing a deflection rate switching signal at an output terminal of said first transistor;   means for coupling said deflection rate switching signal to said output switching means for generating said first and second deflection intervals;   a second transistor of a conductivity type complementary to that of said first transistor and coupled to said first transistor in an arrangement forming a complementary latch; and   fault signaling means coupled to a fault input terminal of said complementary latch and responsive to a fault condition occurrence within said deflection circuit for energizing said complementary latch for disabling said output switching means by preventing said first transistor from changing conductive states.   
     
     
       24. A circuit according to claim 23, wherein the collector of said first transistor is coupled to the base of said second transistor and the collector of said second transistor is coupled to the base of said first transistor for forming a regenerative path. 
     
     
       25. A circuit according to claim 24, wherein said first transistor comprises a horizontal oscillator and said output switching means comprises a horizontal output transistor. 
     
     
       26. A circuit according to claim 25, wherein said deflection circuit includes a flyback transformer for generating an ultor voltage. 
     
     
       27. A circuit according to claim 26, wherein said fault signaling means comprises means for detecting retrace pulses developed in said flyback transformer.