Semiconductor apparatus

Abstract

A field-effect transistor device is provided having a relatively substantial capability to withstand reverse bias voltages. The device can also be provided having a relatively low "on" condition resistance between the source and drain terminals thereof by virtue of the geometrical design used.

The embodiments of the invention in which an exclusive property or right is claimed are defined as follows: 
     
       1. A semiconductor device containing therein a first field-effect transistor device, having a source, drain, gate and substrate, and being capable of withstanding a relatively high voltage between said drain and said substrate and between said drain and said source when in an "off" condition, said field-effect transistor device comprising: a semiconductor material body of a first conductivity type, in at least some parts of a first portion thereof serving as said substrate, and having a major surface where said first body portion intersects said major surface to form a first major surface portion, said first body portion having a first dopant distribution therein leading to said first conductivity type where said first dopant has a maximum concentration of less than 5 × 10 15  atoms per cubic centimeter except in a threshold voltage adjust surface region adjacent to said first major surface portion wherein a selected first dopant threshold adjust surface region distribution is provided;   a first drain region of a second conductivity type located in said first body portion and intersecting said first major surface portion, said first drain region having a second dopant net distribution therein for said second dopant in excess of said first dopant in said threshold voltage adjust surface region leading to said second conductivity type which is so distributed by having passed a maximum of 1 × 10 13  atoms of said second dopant per unit area through said intersection of said first drain region and said first major surface portion in excess of those first dopant atoms present immediately adjacent to this said intersection;   a first source region of said second conductivity type located in said first body portion and intersecting said first major surface portion, said first source region being spaced apart from said first drain region in said first major surface portion;   a first gate conductive means separated from said first major surface portion by a first insulating layer of a first thickness and located across said first insulating layer from that space occurring between said first drain and first source regions in said first major surface portion;   a drain region interconnection means in electrical contact with said first drain region; and   a source region interconnection means in electrical contact with said first source region.   
     
     
       2. The device of claim 1 wherein said drain region interconnection means and said source region interconnection means are each of heavily doped polycrystalline silicon and said semiconductor material body is of doped silicon. 
     
     
       3. The device of claim 3 wherein said drain region interconnection means and said source region interconnection means each have a layer of platinum making said electrical contact to said first drain and first source regions, respectively, through platinum silicide material. 
     
     
       4. The device of claim 1 wherein said first source region has a third dopant distribution therein leading to said second conductivity type which is substantially identical to said second dopant distribution. 
     
     
       5. The device of claim 1 wherein there is contained another transistor device. 
     
     
       6. The device of claim 1 wherein there is further comprised: a first plurality of regions of a second conductivity type, including a selected one of said first drain and said first source regions, each located in said semiconductor material body in such a manner as to intersect said first major surface portion in a first plurality of triangular surface portions completely separated in said first major surface portion and at least partly so by a first surface mesh formed by other portions of said first body portion, each said triangular surface portion in said first plurality thereof having each of those edges serving as boundaries thereof, including an outer edge, substantially parallel to one edge in every other triangular surface portion in said first plurality of triangular surface portions, said first plurality of triangular surface portions being arranged along a first direction in said first major surface portion such that each said outer edge in each said triangular surface portion in said first plurality thereof is substantially parallel to said first direction; and   a second pluarlity of regions of said second conductivity type located in said semiconductor material body in such a manner as to intersect said first major surface portion in a second plurality of triangular surface portions completely separated in said first major surface portion and at least partly so separated by a second surface mesh formed by other portions of said semiconductor material body, each said triangular surface portion in said second plurality thereof having each of those edges serving as boundaries thereof, including an outer edge, substantially parallel to one edge in every other triangular surface portion in said second plurality of triangular surface portions, said second plurality of triangular surface portions being arranged along said first direction such that each said outer edge in each said triangular surface portion in said second plurality thereof is substantially parallel to said first direction, said first and second pluralities of triangular surface portions being adjacent but spaced apart from one another in said first major surface portion by portions of said first and second meshes with an outer edge of every other triangular surface portion in first plurality thereof being located just across said spacing from an outer edge of a triangular surface portion in said second plurality thereof.   
     
     
       7. The device of claim 1 wherein there is further comprised a plurality of regions, including a selected one of said first source and said first drain regions, located in said semiconductor material body in such a manner that each intersects said first major surface portion in a triangular surface portion with every said triangular surface portion being completely separated at said first major surface portion from one another, there being interposed therebetween a separating surface in said first major surface portion formed by other portions of said first body portion, and further, with said separating surface being associated so that all of said separating surface may be viewed as being apportioned for assignment to an associated one of said triangular surface portions in a manner to form extended triangular portions each containing therein its associated said triangular surface portion, said triangular surface portions being arranged with respect to one another in such a manner that said associated extended triangular surface portions form a densely packed hexagonal matrix structure. 
     
     
       8. The device of claim 1 wherein there is further comprised: a mesh surface in said first major surface portion with at least a portion of said mesh surface formed as an intersecting network in a mesh pattern having trinagular openings; and   a plurality of regions, including a selected one of said first source and said first drain regions, each located to have a surface thereof contained completely within one of said triangular openings.   
     
     
       9. The device of claim 1 wherein there is further comprised: a first plurality of regions of a second conductivity type, including a selected one of said first drain and said first source regions, each located in said semiconductor material body in such a manner as to intersect said first major surface portion in a first plurality of quadrilateral surface portions completely separated in said first major surface portion and at least partly so by a first surface mesh formed by other portions of said first body portion, each said quadrilateral surface portion in said first plurality thereof each of those edges serving as boundaries thereof, including an outer edge, substantially parallel to one edge in every other quadrilateral surface portion in said first plurality of quadrilateral surface portions, said first plurality of quadrilateral surface portions being arranged along a first direction in said first major surface portion such that each said outer edge in each said quadrilateral surface portion in said first plurality thereof is substantially parallel to said first direction; and   a second plurality of regions of said second conductivity type located in said semiconductor material body in such a manner as to intersect said first major surface portion in a second plurality of quadrilateral surface portions completely separated in said first major surface portion and at least partly so separated by a second surface mesh formed by other portions of said semiconductor material body, each said quadrilateral surface portion in said second plurality thereof having each of those edges serving as boundaries thereof, including an outer edge, substantially parallel to one edge in every other quadrilateral surface portion in said second plurality of quadrilateral surface portions, said second plurality of quadrilateral surface portions being arranged along said first direction such that each said outer edge in each said quadrilateral surface portion in said second plurality thereof is substantially parallel to said first direction, said first and second pluralities of quadrilateral surface portions being adjacent but spaced apart from one another in said first major surface portion by portions of said first and second meshes with an outer edge of every other quadrilateral surface portion in first plurality thereof being located just across said spacing from an outer edge of a quadrilateral surface portion in said second plurality thereof.   
     
     
       10. The device of claim 1 wherein there is further comprised a plurality of source and drain regions, including a selected one of said first source and said first drain regions, located in said semiconductor material body in such a manner that each intersects said first major surface portion in a quadrilateral surface portion with every said quadrilateral surface portion being completely separated at said first major surface portion from one another, there being interposed therebetween a separating surface in said first major surface portion formed by other portions of said first body portion, and further, with said separating surface being associated so that all of said separating surface may be viewed as being apportioned for assignment to an associated one of said quadrilateral surface portions in a manner to form extended quadrilateral portions each containing therein its associated said quadrilateral surface portion, said quadrilateral surface portions being arranged with respect to one another in such a manner that said associated extended quadrilateral surface portions form a densely packed rectangular matrix structure. 
     
     
       11. The device of claim 1 wherein there is further comprised: a mesh surface in said first major surface portion with at least a portion of said mesh surface formed as an intersecting network in a mesh pattern having quadrilateral openings; and   a plurality of regions, including a selected one of said first source and said first drain regions, each located to have a surface thereof contained completely within one of said quadrilateral openings.   
     
     
       12. The device of claim 6 wherein said source region has a third dopant distribution therein leading to said second conductivity type which is substantially identical to said second dopant distribution. 
     
     
       13. The device of claim 6 wherein there is contained another transistor device. 
     
     
       14. The device of claim 6 wherein said triangular surface portions are formed as equilateral triangles. 
     
     
       15. The device of claim 7 wherein said source region has a third dopant distribution therein leading to said second conductivity type which is substantially identical to said second dopant distribution. 
     
     
       16. The device of claim 7 wherein there is contained another transistor device. 
     
     
       17. The device of claim 7 wherein said triangular surface portions are formed as equilateral triangles. 
     
     
       18. The device of claim 8 wherein said first source region has a third dopant distribution therein leading to said second conductivity type which is substantially identical to said second dopant distribution. 
     
     
       19. The device of claim 8 wherein there is contained another transistor device. 
     
     
       20. The device of claim 8 wherein said triangular openings are formed as equilateral triangles. 
     
     
       21. The device of claim 9 wherein said first source region has a third dopant distribution therein leading to said second conductivity type which is substantially identical to said second dopant distribution. 
     
     
       22. The device of claim 9 wherein there is contained another transistor device. 
     
     
       23. The device of claim 9 wherein said quadrilateral surface portions are formed as squares. 
     
     
       24. The device of claim 10 wherein said first source region has a third dopant distribution therein leading to said second conductivity type which is substantially identical to said second dopant distribution. 
     
     
       25. The device of claim 10 wherein there is contained another transistor device. 
     
     
       26. The device of claim 10 wherein said quadrilateral surface portions are formed as squares. 
     
     
       27. The device of claim 11 wherein said first source region has a third dopant distribution therein leading to said second conductivity type which is substantially identical to said second dopant distribution. 
     
     
       28. The device of claim 11 wherein there is contained another transistor device. 
     
     
       29. The device of claim 11 wherein said quadrilateral openings are formed as squares. 
     
     
       30. A semiconductor device containing therein a first field-effect transistor device having a source, drain and gate, and being capable of withstanding a relatively high voltage between said drain and said substrate and between said drain and said source when in an "off" condition, said field-effect transistor device comprising: a semiconductor material body of a first conductivity type, in at least some parts of a first portion thereof serving as said substrate, and having a major surface where said first body portion intersects said major surface to form a first major surface portion, said first body portion having a first dopant distribution therein leading to said first conductivity type;   a first drain region of a second conductivity type located in said first body portion and intersecting said first major surface portion with a first drain pn junction separating said first drain region and remaining parts of said first body portion, said first drain region having a second dopant distributed therein leading to said conductivity type;   a first source region of said second conductivity type located in said first body portion and intersecting said first major surface portion, said first source region being spaced apart from said first drain region in said first major surface portion;   a first gate conductive means separated from said first major surface portion by a first insulating layer of a first thickness and located across said first insulating layer from that space occurring between said first drain and first source regions in said first major surface portion, with concentrations of said first and second dopants and said first insulating layer thickness being such that a reverse bias voltage applied across said first drain pn junction can be sufficiently large to form a depletion region in said first drain region which extends completely through said first drain region without breakdown occurring across said first drain pn junction;   a drain region interconnection means in electrical contact with said first drain region; and   a source region interconnection means in electrical contact with said first source region.   
     
     
       31. The device of claim 30 wherein said drain region interconnection means and said source region interconnection means are even heavily doped polycrystalline silicon and said semiconductor material body is of doped silicon. 
     
     
       32. The device of claim 30 wherein said drain region interconnection means and said source region interconnection means each have a layer of platinum making said electrical contact to said first drain and first source regions, respectively, through platinum silicide material. 
     
     
       33. The device of claim 30 wherein said first source region has a third dopant distribution therein leading to said second conductivity type which is substantially identical to said second dopant distribution. 
     
     
       34. The device of claim 30 wherein there is contained another transistor device. 
     
     
       35. The device of claim 30 wherein there is further comprised: a first plurality of regions of a second conductivity type, including a selected one of said first drain and said first source regions, each located in said semiconductor material body in such a manner as to intersect said first major surface portion in a first plurality of triangular surface portions completely separated in said first major surface portion and at least partly so by a first surface mesh formed by other portions of said first body portion, each said triangular surface portion in said first plurality thereof having each of those edges serving as boundaries thereof, including an outer edge, substantially parallel to one edge in every other triangular surface portion in said first plurality of triangular surface portions, said first plurality of triangular surface portion being arranged along a first direction in said first major surface portion such that each said outer edge in each said triangular surface portion in said first plurality thereof is substantially parallel to said first direction; and   a second plurality of regions of said second conductivity type located in said semiconductor material body in such a manner as to intersect said first major surface portion in a second plurality of triangular surface portions completely separated in said first major surface portion and at least partly so by a second surface mesh formed by other portions of said semiconductor material body, each said triangular surface portion in said second plurality thereof having each of those edges serving as boundaries thereof, including an outer edge, substantially parallel to one edge in every other triangular surface portion in said second plurality of triangular surface portions, said second plurality of triangular surface portions being arranged along said first direction such that each said outer edge in each said triangular surface portion in said second plurality thereof is substantially parallel to said first direction, said first and second pluralitites of triangular surface portions being adjacent but spaced apart from one another in said first major surface portion by portions of said first and second meshes with an outer edge of every other triangular surface portion in first plurality thereof being located just across said spacing from an outer edge of a triangular surface portion in said second plurality thereof.   
     
     
       36. The device of claim 30 wherein there is further comprised a plurality of source and drain regions, including a selected one of said first source and said first drain regions located in said semiconductor material body in such a manner that each intersects said first major surface portion in a trinagular surface portion with every said triangular surface portion being completely separated at said first major surface portion from one another, there being interposed therebetween a separating surface in said first major surface portion formed by other portions of said first body portion, and further, with said separating surface being associated so that all of said separating surface may be viewed as being apportioned for assignment to an associated one of said triangular surface portions in a manner to form extended triangular portions each containing therein its associated said triangular surface portion, said triangular surface portions being arranged with respect to one another in such a manner that said associated extended triangular surface portions form a densely packed hexagonal matrix structure. 
     
     
       37. The device of claim 30 wherein there is further comprised: a mesh surface in said first major surface portion with at least a portion of said mesh surface formed as an intersecting network in a mesh pattern having triangular openings; and   a plurality of regions, including a selected one of said first source and said first drain regions, each located to have a surface thereof contained completely within one of said triangular openings.   
     
     
       38. The device of claim 30 there is further comprised: a first plurality of regions of a second conductivity type, including a selected one of said first drain and said first source regions, each located in said semiconductor material body in such a manner as to intersect said first major surface portion in a first plurality of quadrilateral surface portions completely separated in said first major surface portion and at least partly so by a first surface mesh formed by other portions of said first body portion, each said quadrilateral surface portion in said first plurality thereof having each of those edges serving as boundaries thereof, including an outer edge, substantially parallel to one edge in every other quadrilateral surface portion in said first plurality of quadrilateral surface portions, said first plurality of quadrilateral surface portions being arranged along a first direction in said first major surface portion such that each said outer edge in each said quadrilateral surface portion in said first plurality thereof is substantially parallel to said first direction; and   a second plurality of regions of said second conductivity type located in said semiconductor material body in such a manner as to intersect said first major surface portion in a second plurality of quadrilateral surface portions completely separated in said first major surface portion and at least partly so by a second surface mesh formed by other portions of said semiconductor material body, each said quadrilateral surface portion in said second plurality thereof having each of those edges serving as boundaries thereof, including an outer edge, substantially parallel to one edge in every other quadrilateral surface portion in said second plurality of quadrilateral surface portions, said second plurality of quadrilateral surface portions being arranged along said first direction such that each said outer edge in each said quadrilateral surface portion in said second plurality thereof is substantially parallel to said first direction, said first and second pluralities of quadrilateral surface portions being adjacent but spaced apart from one another in said first major surface portion by portions of said first and second meshes with an outer edge of every other quadrilateral surface portion in first plurality thereof being located just across said spacing from an outer edge of a quadrilateral surface portion in said second plurality thereof.   
     
     
       39. The device of claim 30 wherein there is further comprised a plurality of source and drain regions, including a selected one of said first source and said first drain regions, located in said semiconductor material body in such a manner that each intersects said first major surface portion in a quadrilateral surface portion with every said source and said drain quadrilateral surface portion being completely separated at said first major surface from one another, there being interposed therebetween a separating surface in said first major surface portion formed by other portions of said first body portion, and further, with said separating surface being associated so that all of said separating surface may be viewed as being apportioned for assignment to an associated one of said quadrilateral surface portions in a manner to form extended quadrilateral portions each containing therein its associated said quadrilateral surface portion, said quadrilateral surface portions being arranged with respect to one another in such a manner that said associated extended quadrilateral surface portions form a densely packed rectangular matrix structure. 
     
     
       40. The device of claim 30 wherein there is further comprised: a mesh surface in said first major surface portion with at least a portion of said mesh surface formed as an intersecting network in a mesh pattern having quadrilateral openings; and   a plurality of regions, including a selected one of said first source and said first drain regions, each located to have a surface thereof contained completely within one of said quadrilateral openings.   
     
     
       41. The device of claim 35 wherein said first source region has a third dopant distribution therein leading to said second conductivity type which is substantially identical to said second dopant distribution. 
     
     
       42. The device of claim 35 wherein there is contained another transistor device. 
     
     
       43. The device of claim 35 wherein said triangular surface portions are formed as equilateral triangles. 
     
     
       44. The device of claim 36 wherein said first source region has a third dopant distribution therein leading to said second conductivity type which is substantially identical to said second dopant distribution. 
     
     
       45. The device of claim 36 wherein there is contained another transistor device. 
     
     
       46. The device of claim 36 wherein said triangular surface portions are formed as equilateral triangles. 
     
     
       47. The device of claim 37 wherein said first source region has a third dopant distribution therein leading to said second conductivity type which is substantially identical to said second dopant distribution. 
     
     
       48. The device of claim 37 wherein there is contained another transistor device. 
     
     
       49. The device of claim 37 wherein said triangular openings are formed as equilateral triangles. 
     
     
       50. The device of claim 38 wherein said first source region has a third dopant distribution therein leading to said second conductivity type which is substantially identical to said second dopant distribution. 
     
     
       51. The device of claim 38 wherein there is contained another transistor device. 
     
     
       52. The device of claim 38 wherein said quadrilateral surface portions are formed as squares. 
     
     
       53. The device of claim 39 wherein said first source region has a third dopant distribution therein leading to said second conductivity type which is substantially identical to said second dopant distribution. 
     
     
       54. The device of claim 39 wherein there is contained another transistor device. 
     
     
       55. The device of claim 39 wherein said quadrilateral surface portions are formed as squares. 
     
     
       56. The device of claim 40 wherein said first source region has a third dopant distribution therein leading to said second conductivity type which is substantially identical to said second dopant distribution. 
     
     
       57. The device of claim 40 wherein there is contained another transistor device. 
     
     
       58. The device of claim 40 wherein said quadrilateral openings are formed as squares.