Parallel run-length decoder

Abstract

System and method for parallel decoding of character data in run length format to produce data in dot matrix form for presentation to a display device. The data for successive runs is stored in registers and processed in parallel to provide address data for memory devices programmed to deliver predetermined output data patterns in response to the address data.

What is claimed is: 
     
       1. A decoder for parallel conversion of binary run length data to a dot matrix format for presentation to a display, comprising: register means for storing binary coded data representing the lengths of successive runs of dots to be displayed, output means for selectively delivering predetermined patterns of output data in the dot matrix format in accordance with input signals applied thereto, and means responsive concurrently to a plurality of digits of the coded data in the register means for applying input signals to the output means to cause said means to deliver output data patterns for runs of the lengths represented by the coded data. 
     
     
       2. The decoder of claim 1 wherein the output means comprises a programmable read only memory. 
     
     
       3. The decoder of claim 1 wherein the means for applying input signals to the output means comprises a plurality of binary adders connected in a tree network between the register means and the output means. 
     
     
       4. In a system for generating characters for display in a dot matrix format on a medium scanned in discrete lines: means for providing coded number data representing the lengths of successive runs of dots in each scan line passing through a character, means for decoding a plurality of the digits of the number data in parallel, and means for providing output data patterns in the dot matrix format for presentation to the display medium. 
     
     
       5. The system of claim 4 wherein the means for providing output data patterns includes a memory device programmed to provide predetermined output data patterns in response to predetermined address inputs, and said means for decoding includes means responsive to the coded data for applying address inputs to the memory device, whereby the data patterns produced by the output device correspond to the coded data. 
     
     
       6. In a decoder for converting binary coded run length data to a dot matrix format for display on a medium scanned in discrete lines: a plurality of input registers, means for applying the data for successive runs to successive ones of the registers, memory means programmed to provide predetermined output data patterns in the dot matrix format in response to address inputs applied thereto, and a plurality of binary adders connected in a tree network between the input registers and the memory means for parallel processing of the run length data to provide address inputs for the memory means. 
     
     
       7. The decoder of claim 6 wherein the memory means comprises a plurality of programmable read only memories (PROM's) and means for combining the outputs of the PROM's in a logical OR function. 
     
     
       8. The decoder of claim 6 wherein successive portions of the data are decoded during successive clock cycles, together with means for clearing the register for each run when all of the data for that run has been decoded. 
     
     
       9. The decoder of claim 6 wherein successive portions of the data are decoded during successive clock cycles and the means for applying the data to each input register includes means for replacing the data for a partially decoded run with the portion of the data yet to be decoded for that run.