Data processor with improved cyclic data buffer apparatus

Abstract

Apparatus for designating contiguous memory locations in a data memory as a circular data buffer. A limit register defines the topmost buffer location and a modulus register defines the length of the buffer. Circuitry detects violations of the upper boundary of the buffer and subtracts the buffer length from the address. Boundary violation circuitry also controls conditional execution of a data processor instruction which conditionally subtracts the buffer length from the address.

What is claimed is: 
     
       1. For use with a data processor, apparatus for defining a circular data buffer in a random access data memory comprising: first means for storing the addresses of the topmost location of said buffer,   second means for storing the number of locations comprising said buffer,   means for applying a first address,   means responsive to said means for applying and to said first means for storing for determining if said first address is greater than said address of the topmost location, and   means comprising said data processor responsive to said means for determining and to said second means for storing for arithmetically altering said first address.   
     
     
       2. Apparatus as set forth in claim 1 further comprising means responsive to said data processor for accessing a random access data memory with said first address so arithmetically altered.   
     
     
       3. For use with a data processor, apparatus for defining a circular data buffer in a random access data memory comprising: first means for storing the addresses of the topmost location of said buffer,   second means for storing the number of locations comprising said buffer,   means for applying a first address,   means responsive to said means for applying and to said first means for storing for determining if said first address is greater than said address of the topmost location, and   means responsive to said means for determining and to said second means for storing for arithmetically altering said first address, said means for arithmetically altering comprising   said data processor, and   means responsive to said second means for storing for subtracting said number of locations from said first address.   
     
     
       4. Apparatus as set forth in claim 3 further comprising means responsive to said means for arithmetically altering for accessing a random access data memory with said first address so arithmetically altered.   
     
     
       5. Apparatus for use with a data processor comprising: a limit register loadable with information under control of said data processor,   a modulus register loadable with information under control of said data processor,   a comparator for comparing an address with the contents of said limit register,   an arithmetic circuit responsive to said comparator for arithmetically altering said address by the contents of said modulus register, and   means responsive to said comparator for controlling the execution of instructions by said data processor.   
     
     
       6. Apparatus as set forth in claim 5 further comprising means responsive to said comparator and to said data processor for controlling the execution of instructions by said data processor.