Electrically programmable logic array

Abstract

A write once, read only electrically programmable storage circuit is disclosed, which employs a flip-flop circuit to store the programmed conductive state of the array device, by means of a blocking transistor connected between the array device and one node of the flip-flop, the control electrode of the blocking transistor being connected to the other node of the flip-flop. With the flip-flop having an initial first state so that the blocking device is conductive, a precharged signal may be conducted through the array device to ground indicating a first stored information state. By driving a write signal through the array device and the blocking device, of sufficient magnitude to set the flip-flop in its opposite state, the blocking device is then made nonconductive and subsequent attempts to transmit a precharge signal through the array device to ground, will not be possible, indicating a second stored information state. This basic storage circuit is inclined as the array cell in a programmable PLA chip architecture which requires only four additional pins beyond the mask programmable version. This is accomplished by the dual use of the output latches of the OR array for both reading out the array and for programming the array by a scan-in technique. Cells in the AND array are programmed by a product term programmer register which allows product terms to be programmed by input partitioning circuits.

Having thus described our invention, what we claim as new, and desire to secure by Letters Patent is: 
     
       1. A memory circuit, comprising: a transistor flip flop circuit having a first active device with its current path connected between a first node and a zero state voltage and a second active device with its current path connected between a second node and said zero state voltage, said first node connected to the control electrode of said second active device and said second node connected to the control electrode of said first active device, with said first device having an initial nonconductive state and said second device having an initial conductive state;   a blocking transistor device having its current path connected to said second node and its control electrode connected to said first node;   an array transistor device having its current path connected between the current path of said blocking transistor and a word line and its control electrode connected to a bit line;   a circuit path from said word line through the current paths of said array device, said blocking device, and said second active device representing a first stored information state, a second information state being represented by an open circuit due to said blocking device being nonconductive;   said conduction state of said blocking device being controlled by the voltage state of said first node;   said voltage state at said first node being selectably altered from said first state with said first active device nonconductive to a second state with said first active device conductive, by the transmission of a write voltage signal from said word line through the current paths of said array device and blocking device to said control electrode of said first active device turning it on and thus switching the flip-flop and turning said blocking device off.   
     
     
       2. The circuit of claim 1 wherein said first and second active devices and said blocking and array devices are field effect transistors. 
     
     
       3. The circuit of claim 1 wherein said first and second active devices and said blocking and array devices are bipolar transistors. 
     
     
       4. The circuit of claim 1 wherein said flip-flop circuit is an asymmetric bistable circuit wherein said first active device enters a nonconductive state and said second active device enters a conductive state when operating power is initially applied to said flip-flop circuit. 
     
     
       5. The circuit of claim 1 wherein said flip-flop circuit further comprises: an electrode connecting said first node of said flip-flop to an initializing signal source for turning said second active device on and said first active device off at an initialization time.   
     
     
       6. A programmable read only memory architecture, comprising: an array of storage cells having rows and columns, each row connected to a respective input line and each column connected to a respective output line, said cells having first and second storage states which are programmable through their respective output lines;   a plurality of output latches, each having a first input connected to one of said output lines, for storing the stored state of accessed ones of said storage cells in a read mode;   said plurality of output latches each having a second input for storing a programming pulse and having a feedback path connected to each corresponding output line, for transmitting said programming pulse to said selected 1's of said storage cells;   whereby said output latch has a second function of programming said storage cells.   
     
     
       7. The programmable read only memory architecture of claim 6, which further comprises: said latches being connected in master/slave configuration to form a shift register, through which a serial stream of both programming is shifted so as to be aligned with the appropriate output line.