Low noise CCD input circuit

Abstract

A "fill and spill" charge coupled device (CCD) input circuit which includes a drain region separated from the input storage region by a potential barrier. The barrier height is held at a level at least as high as that of the potential barrier beneath the first gate electrode and lower than that of the first transfer electrode to insure that carriers injected by the source electrode during the fill operation which might otherwise flow down the CCD channel pass instead to the drain region.

What is claimed is: 
     
       1. A method of operating a CCD in which an input potential well initially is filled by introducing charge therein from a source of charge carriers over a potential barrier, and then some of the charge in the well is spilled out of the well to leave remaining in the well an amount of charge which is a function of a signal potential between the electrode employed to form the barrier and the electrode employed to form the well, comprising the step of: removing from the well during the filling thereof any carriers which attempt to fill the well to a level greater by more than a substantially fixed percentage, than the height of said potential barrier.   
     
     
       2. A CCD input electrode structure comprising, in combination: a semiconductor substrate of one conductivity type;   a first region in the substrate of a conductivity opposite to that of the substrate;   first, second and third electrodes insulated from the substrate, said second electrode comprising a storage electrode, said first electrode located between said storage electrode and said first region and operating as a gate electrode, and said third electrode adjacent to said second electrode;   means for applying a bias voltage to said first electrode for forming a first potential barrier in said substrate;   means including means for applying an input signal voltage between said first and second electrodes for forming a potential well in the region of said substrate beneath said second electrode;   means for applying a voltage to said third electrode for forming a second potential barrier in said substrate which is higher than said first potential barrier;   a drain region in the substrate for conducting away charge carriers;   a fourth electrode insulated from the substrate located between said drain region and said second electrode;   means responsive to the bias voltage applied to said first electrode for supplying a portion thereof to said fourth electrode for creating a third potential barrier in said substrate which is at least as high as said first potential barrier and lower than said second potential barrier; and   means for placing said source electrode at a first voltage level such that charge carriers flow over said first potential barrier into said first potential well, whereby any such carriers which overflow said third potential barrier flow to said drain region, and for then withdrawing from said well that portion of the charge filling the well to a level greater than that of said first potential barrier.   
     
     
       3. A CCD input electrode structure as set forth in claim 2, wherein said means for placing said source electrode at a first voltage level comprises a current source. 
     
     
       4. A CCD input electrode structures as set forth in claim 2, wherein said means responsive to said bias voltage comprises means for creating said third potential barrier at a higher level than said first potential barrier and lower than said second potential barrier. 
     
     
       5. A CCD input electrode structure as set forth in claim 2, wherein said means responsive to said bias potential comprises a voltage divider. 
     
     
       6. In a charge coupled circuit which includes a semiconductor substrate, source electrode means in the substrate, storage electrode means insulated from the substrate, and first gate electrode means insulated from the substrate and located between the storage electrode means and said source electrode means for controlling the flow of charge between the source electrode means and the substrate region beneath the storage electrode means, in combination: means coupled to said first gate electrode means and to said storage electrode means, including means for applying between said first gate electrode means and said storage electrode means a signal potential which may vary, and means supplying a bias potential, for creating a first potential well beneath the storage electrode means and a shallower second potential well beneath the gate electrode means;   a drain electrode in said substrate;   second gate electrode means insulated from the substrate, this one located between said storage electrode means and said drain electrode for controlling the flow of charge between said first potential well and said drain electrode;   means responsive to said bias potential for creating beneath said second gate electrode means a third potential well somewhat shallower than said second potential well;   means for creating a potential difference between said source electrode means and said storage electrode means, during a first time period, for causing a flow of charge from said source electrode means to said first potential well in an amount independent of said signal potential; and   means for changing and potential difference between said storage electrode means and said source electrode means, during a second time period following the first in a sense to return charge from the potential well beneath said storage electrode means to said source electrode means to an extent to leave stored beneath said storage electrode means an amount of charge dependent on said signal potential.   
     
     
       7. In a charge coupled circuit as set forth in claim 6, wherein said means responsive to said bias potential comprises means for applying a fixed percentage of said bias potential to said second gate electrode means. 
     
     
       8. In a charge coupled circuit as set forth in claim 7, said means responsive to said bias potential comprising a voltage divider. 
     
     
       9. In a charge coupled circuit as set forth in claim 6, further including: a plurality of transfer electrodes insulated from the substrate and adjacent to one another forming together a charge coupled device channel, said electrodes for receiving multiple phase voltages for propagating charge signal, the first of said electrodes being located adjacent to said storage electrode means; and   means for maintaining said first transfer electrode at a voltage level for creating in the substrate a fourth potential well which is shallower than said third potential well, during the period said charge is caused to flow into said potential well and the period charge is returned to said source electrode means.   
     
     
       10. A control circuit for a semiconductor signal charge transfer device, having a substrate formed with an input source region which can supply charge via an input first gate region of said substrate to a first transfer site in said substrate in response to applied voltages, which comprises: storage electrode means adjacent to said first transfer site for controlling the latters potential;   first gate electrode means adjacent to said input first gate region for controlling the latters potential;   first circuit means for applying voltages to said storage electrode means and to said gate electrode means, said first circuit means including means for applying a signal voltage whose value may vary between said storage electrode means and said gate electrode means, for creating a potential well at the first transfer site, and a shallower potential well at said input gate region;   a drain region in said substrate;   a second gate region of said substrate extending between said drain region and said first transfer site;   second gate electrode means adjacent to said second gate region for controlling the latters potential;   second circuit means for applying a bias voltage to said second gate electrode means for creating a shallower potential well at said second gate region than at said first gate region;   third circuit means for applying a charge injecting voltage pulse between said input source and said storage electrode means for a first time period, of an amplitude sufficient for the transport of a predetermined signal-independent charge from said source region to said potential well of said first transfer site and for then removing said pulse, whereby charge tends to return from said first transfer site to said input source region;   means for continuing to apply said signal voltage between said gate electrode means and said storage electrode means during a second time period immediately following said first time period and which outlasts said first time period, for controlling the retransportation of said signal-independent charge from the first transfer site through the gate region back to the input source during said second time period, in accordance with said signal voltage;   a second transfer site in said substrate adjacent to said first transfer site;   transfer electrode means adjacent to said second transfer site for controlling the latters potential; and   fourth circuit means for applying a bias voltage to said transfer electrode during said first and second time periods for creating a shallower potential well at said second transfer site than at said second gate region.   
     
     
       11. In an input circuit for a CCD which includes a substrate: an input region in the substrate of opposite conductivity than the substrate; a gate region of the substrate adjacent to the input region; a storage region of the substrate adjacent to the gate region; means including electrodes over said gate and storage regions, a signal source coupled between said electrodes, and a bias voltage source connected to said electrode over said gate region, for producing a shallower potential well in said gate region that in said storage region; and means for filling said potential well beneath said electrode over said storage region comprising means for applying a voltage to said input region for causing the same to emit charge carriers which pass through said shallower well to the potential well in said storage region, the improvement comprising: means responsive to the voltage applied to said electrode over said gate region for maintaining said input region at a voltage level which is a fixed percentage of that at said electrode over said gate region during the period said potential well of said storage region is being filled.