Digital multiplexing and demultiplexing system

Abstract

A digital multiplexing and demultiplexing system for time division multiplexing a number of incoming plesiosynchronous low rate component signals and a number of incoming plesiosynchronous intermediate rate component signals into an outgoing single high rate signal. A first multiplexing stage time stores and stuffs the low rate component signals and multiplexes them into synchronous intermediate rate signals. A second multiplexing stage stores and stuffs the plesiosynchronous and synchronous intermediate rate signals and multiplexes them into the outgoing high rate signal.

What we claim is: 
     
       1. A digital multiplexing and demultiplexing system in which incoming plesiosynchronous signals are time multiplexed bit by bit into synchronous intermediate rate signals and a number of incoming plesiosynchronous intermediate rate signals are time multiplexed bit by bit with said synchronous intermediate rate signals into an outgoing signal high rate signal having a high rate which is a multiple of the originating intermediate rates, said plesiosynchronous low rate signals and said plesiosynchronous intermediate rate signals comprising only information bits and said synchronous intermediate rate signals and said high rate signal comprising information bits, stuffing bits and filling bits including framing bits, service bits and stuffing indication bits arranged in predetermined bit positions in frames, the system comprising; (a) first means for storing and stuffing said incoming plesiosynchronous low rate component signals in dependence upon the difference between their own originating respective low rates and said predetermined low rate;   (b) multiplexing means receiving and multiplexing said predetermined low rate stuffed signals into frames of said synchronous intermediate rate signals;   (c) means for filling into said synchronous intermediate rate signals a first number of filling bits of predetermined addresses of the frame forming synchronous intermediate rate filled signals;   (d) second means for storing said synchronous intermediate rate filled signals and third means for storing said incoming plesiosynchronous intermediate rate component signals;   (e) second means for stuffing said stored synchronous intermediate rate filled signals and third means for stuffing said stored plesiosynchronous intermediate rate component signals in dependence upon the difference between the originating intermediate rates and said predetermined intermediate rate;   (f) multiplexing means connected to said second and third stuffing means for multiplexing the predetermined intermediate rate stuffed signals into frames of the high rate signals;   (g) means for filling into said high rate signal a second number of filling bits in bit positions of predetermined addresses of the frame thereof and thereby forming a high rate filled signals;   (h) first demultiplexing means receiving and demultiplexing said high rate filled signal into first and second numbers of synchronous intermediate rate signals;   (i) first storing and unstuffing means for storing the first number of synchronous intermediate rate demultiplexed signals and for extracting filling bits of predetermined addresses of high rate signal frame and for unstuffing into synchronous intermediate rate filled signals;   (j) second storing and unstuffing means for storing the second number of synchronous intermediate rate demultiplexed signals for extracting filling bits of predetermined addresses of high rate signal frames and for unstuffing into outgoing plesiosynchonous intermediate rate component signals;   (k) second demultiplexing means receiving and demultiplexing said synchronous intermediate rate filled signals read out of said first storing and unstuffing means into synchronous low rate singnals;   (l) third storing and unstuffing means for storing synchronous low rate signals and for extracting filling bits of predetermined addresses of intermediate rate signal frames and for unstuffing into outgoing plesiosynchronous low rate component signals;   (m) interchangeable assembling means for replacing a group of incoming and outgoing plesiosynchronous low rate component signals by two incoming and outgoing plesiosynchonous intermediate rate component signals in said high rate filled signal; and   (n) said assembling means including separate storing means for incoming low rate signals and for intermediate rate signals and further including interconnecting mean between said separate storing mean and said first, second and third storing and unstuffing means.