Method for producing a single transistor storage cell

Abstract

For the production of V-MOS single transistor storage cells at the surface of a silicon crystal of first conductivity type, two adjoining zones of opposite conductivity type can first be produced by masked diffusion or implantation. Then, with the use of a correspondingly oriented etching mask, a funnel-shaped depression is produced at the semiconductor surface such that the two zones of opposite conductivity type are separated from one another but reach the surface of the silicon crystal within the funnel-shaped depression. This depression is then coated with a thin SiO 2 layer which is provided as a carrier of the gate electrode of the field effect transistor which forms the storage cell. The two zones of the opposite conductivity type, now separated, are used as a source and as a drain and also as a storage capacitance. For geometric reasons, the two zones of opposite conductivity type can only be produced one after the other with the use of corresponding doping masks. A mask is additionally required in order to produce the funnel-shaped depression. The masks must be carefully adjusted in relation to one another. In order to eliminate the need for an additional mask, one of the masks used for the production of the zones of opposite conductivity type is employed without change as an etching mask for the production of the funnel-shaped depression. The layer forming the doping mask must then, in addition to its impermeability for the doping material utilized, also be resistant against the etching compound to be utilized.

I claim as my invention: 
     
       1. A method for producing a single transistor storage cell, comprising the steps of: (a) providing a semiconductor body of first conductivity type and having a major surface;   (b) doping a first zone of second conductivity type opposite to the first conductivity type from said major surface into the semiconductor body to a given depth;   (c) doping through a doping mask window on the major surface a second zone of second conductivity type adjacent and having a contiguous portion with the first zone but to a different depth than the first zone, one of the zones being dimensioned so as to form a pn junction with the semiconductor body which is substantially shorter than a pn junction of the other zone after a V-shaped gate recess is subsequently etched so that a capacitance of the completed storage cell is predominantly provided by the zone with the longer pn junction;   (d) anisotropically etching the V-shaped gate recess by use of the same doping mask window into said second zone, said contiguous portion with the first zone, a portion of the first zone, and a portion of the semiconductor body so as to separate unetched portions of the first and second zones by part of the semiconductor body; and   (e) applying a gate insulation layer and a gate electrode in the V-shaped recess.   
     
     
       2. A method for producing a single transistor storage cell, comprising the steps of: (a) providing a semiconductor body of first conductivity type and having a major surface;   (b) doping a first zone of second conductivity type opposite to the first conductivity type from said major surface into the semiconductor body to a given depth;   (c) doping through a doping mask window on the major surface a second zone of second conductivity type adjacent and having a continguous portion with the first zone and to a depth less than the first zone, one of the zones being dimensioned so as to form a pn junction with the semiconductor body which is substantially shorter than a pn junction of the other zone so that after a V-shaped gate recess is subsequently etched a capacitance of the completed storage cell is predominantly provided by the zone with the longer pn junction;   (d) anisotropically etching the V-shaped gate recess by use of the same doping mask window into said second zone, said contiguous portion with the first zone, a portion of the first zone, and a portion of the semiconductor body so as to separate unetched portions of the first and second zones by part of the semiconductor body; and   (e) applying a gate insulation layer and a gate electrode in the V-shaped recess.   
     
     
       3. A method in accordance with claim 1 including the step of utilizing a thinned alkali caustic solution as an etching compound in order to produce the recess. 
     
     
       4. A method for producing a single transistor storage cell, comprising the steps of: (a) providing a semiconductor body of first conductivity type and having a major surface;   (b) doping a first zone of second conductivity type opposite to the first conductivity type from said major surface into the semiconductor body to a given depth;   (c) providing upper and lower insulating layers on the major surface as a doping mask and doping through a window therein a second zone of second conductivity type adjacent and having a contiguous portion with the first zone but to a greater depth, one of the zones being dimensioned so as to form a pn junction with the semiconductor body which is substantially shorter than a pn junction of the other zone after a V-shaped gate recess is subsequently etched so that a capacitance of the completed storage cell is predominantly provided by the zone with the longer pn junction;   (d) enlarging the window in the lower layer and anisotropically etching the V-shaped gate recess through the window in the upper layer and the enlarged window in the lower layer into said second zone, said contiguous portion with the first zone, a portion of the first zone, and a portion of the semiconductor body so as to separate unetched portions of the first and second zones by part of the semiconductor body; and   (e) applying a gate insulation layer and a gate electrode in the V-shaped recess.   
     
     
       5. A method in accordance with claim 4 including the step of utilizing a thinned alkali caustic solution as an etching compound in order to produce the recess. 
     
     
       6. A method in accordance with claim 4 including the steps of producing the first zone such that it has portions contiguous with the second zone on opposite sides thereof. 
     
     
       7. A method according to claim 4 including the steps of providing the lower insulating layer with a material which can be selectively etched with a medium which attacks neither the upper layer nor the semiconductor body and enlarging the window in the lower layer with said medium. 
     
     
       8. A method in accordance with claim 6 including the step of providing the lower insulating layer as SiO 2 , providing the upper layer as Si 3  N 4 , providing the etching medium to be utilized for widening the doping window in the lower insulating layer as a buffered hydrofluoric acid, and providing an etching medium utilized for producing the recess as a thinned alkali caustic solution.