Apparatus for coordinating real time transfer of data from a processor to a magnetic media device

Abstract

There is disclosed an improved interface apparatus and technique for real time transfer of characters from a text processor to a magnetic card recorder. Characters retrieved from a buffer are subject to reformatting and other operations, the duration of which varies within two character output cycles. The disclosed technique permits time, in effect, to be borrowed from succeeding character cycles. A character is processed and loaded temporarily in a register. The parallel character is then transferred to a serializer register which outputs serial bits to a card writer control for recording on a magnetic card. At the same time this transfer, serialization, and output is occurring the processor is preparing the next character to be written. A character can be output in real time so long as the interval between it and the preceding character is less than two character output cycles in length.

What is claimed is: 
     
       1. In a text processing system, interface apparatus for real time transfer of data between a processor preparing and presenting data at irregular intervals and an output device requiring data at regular intervals wherein the longest processor interval is less than two output intervals, said interface comprising in combination: first buffer means for receiving data from said processor;   second buffer means for receiving data from said first buffer means and connected to said output device;   means for indicating to said processor when transfer of data from said second buffer has begun; and   means responsive to said indicating means for allowing said processor to transfer new data to said first buffer means immediately subsequent to said beginning of transfer from said second buffer whereby said processor is free to initiate processing of a succeeding character.   
     
     
       2. The apparatus of claim 1 further including means for causing transfer of said data to said output means at the beginning of each output cycle provided there has been a transfer of a new data from said processor to said first buffer. 
     
     
       3. The apparatus of claim 2 further including means operative when no new character is in said first buffer at the beginning of an output cycle for causing transfer of a character to said output buffer immediately following the loading of a new character into said first buffer by said processor. 
     
     
       4. The interface apparatus of claim 1 wherein: said buffer means receives data representing one character in parallel format from said processor; and   said second buffer means receives data representing one character in parallel from said first buffer means and transfers said data in serial format to said output device.   
     
     
       5. In a word processing system, apparatus for interfacing between a processor which outputs characters in parallel format at a variable rate and a data utilization device requiring serial data at a constant rate, said apparatus including: a first register for receiving one character at a time from said processor;   a serializer register for receiving a character from said register at the constant rate of the data utilization device and outputting serial bits to said data utilization device;   means indicating each time said serializer register receives a character from said first register,; said indicating means being interrogable by said processor when it has a character ready; and   means for loading said first register when the processor has successfully interrogated said indicating means.