Synthesis arrangements for use in digital data transmission systems

Abstract

In highspeed digital communication systems a number of tributary data streams may be multiplexed into a single main data stream having a higher aggregate data rate. This main data stream contains frame alignment information to achieve correct demultiplexing. In addition pulse justification (pulse stuffing) time slots are provided, catering for the differences in phase and frequency between the individual tributary data and the main data stream, to control the remote oscillators in the demultiplexers. In the event of a data stream failure it is necessary to transmit an alarm indication signal over the failed data stream however the pulse justification equipment attempts to force the bit rate to zero. To overcome this, in the prior art, the data stream is replaced by one generated from a standby oscillator. Significant frequency deviations between the actual data stream when replaced and the injected data stream can be experienced causing substantial controlled oscillator realignment delays to be experienced even for short breaks. The proposal overcomes these problems by providing a shift register storage arrangement which is driven in parallel by the justification signals applied to the tributary data stream under normal operating conditions but does not have any output path. When the data stream fails the contents of the shift register are used to simulate the justification signals. Recirculation of the simulated justification signals also takes place while the data stream failure persists. The size of the simulated sequence (i.e. size of the shift register) determines the accuracy of the controlled oscillator and therefore the realignment delay.

What we claim is: 
     
       1. A justification control signal synthesiser for use in a digital data transmission system employing justification control arrangements, the synthesiser comprising storage means arranged to receive and store the justification control signals of a tributary data stream passing over a data path and upon interruption of the tributary data stream the synthesiser includes means for injecting into the interrupted data stream justification control signals by injecting those signals stored in the storage means on a repetition basis into the data path until the interruption of the tributary data stream ends. 
     
     
       2. A justification control signal synthesiser according to claim 1 in which the storage means comprises a shift register storage arrangement driven in parallel by the justification signals of the tributary data stream with the shift register output path disconnected from the data path. 
     
     
       3. A justification control signal synthesiser according to claim 2 in which the shift register storage arrangement includes means for connecting the shift register output path to the tributary data stream to replace the interrupted justification signals with those stored in the shift register. 
     
     
       4. A justification control signal synthesiser according to claim 3 in which the tributary data stream is connected to the input of a digital switch and the input of the shift register is connected to the output of the digital switch and the digital switch is arranged to pass the tributary data stream from its input to its output and to disconnect the output of the shift register and upon interruption of the tributary data stream the digital switch is arranged to connect the output of the shift register to the output of the digital switch.