I/O Priority resolver

Abstract

Apparatus for resolving the priority of a plurality of input/output devices. The device request signals and signals indicating the channel number of the currently active channel program are applied to the address terminals of a programmable read only memory. Each address location stores bits indicative of the next priority device for the given input conditions.

What is claimed is: 
     
       1. A communication subsystem having a microprocessor and a plurality of communication lines coupled to a U-bus, an M-Bus coupled to said U bus, at least one memory coupled to said M-bus, and I-bus coupled to said U-bus, a plurality of registers coupled to said I-bus, and a priority resolving mechanism coupled to said microprocessor and said communication lines for resolving priority of requesting signal generated by said microprocessor and said plurality of communication lines for requesting access to said at least one memory, said priority resolving mechanism comprising: (a) first means for storing first channel number signal indicative of said microprocessor or one of said communication lines being currently accessing said at least one memory;   (b) programmable read only memory means with a predetermined number of address locations for storing second channel number signals indicative of a next of said microprocessor or one of said communication lines to access said at least one memory, wherein address terminals of said programmable read only memory means are coupled to said microprocessor, said communication lines and said first means for receiving said requesting signals as address signals for addressing one of said predetermined number of address locations;   (c) third means coupled to said programmable read only memory means for receiving said second channel signals from said one of said predetermined address locations for storage in said first means when said currently operating microprocessor or said one of said communication lines has finished accessing said at least one memory.   
     
     
       2. The priority resolving mechanism as recited in claim 1 including address generating means coupled to said programmable read only memory means and responsive to said second channel number signals for generating address signals, said microprocessor being responsive to said address signals for initiating the start of a service routine for enabling said next of said microprocessor or said one of said communication lines to access said at least one memory. 
     
     
       3. The computer system as recited in claim 1 wherein said communication lines are vying for access to said at least one memory, and at least one of said communication lines is operating in a synchronous mode and the remainder of said communication lines having higher priority are operating in an asynchronous mode. 
     
     
       4. The computer system as recited in claim 3 wherein at least two communication lines (a) and (b) respectively are vying for access to said at least one memory and both communication lines are operating in an asynchronous mode, said priority resolving mechanism sotring priority information indicating that said communication line (a) has higher priority.