Data recovery system for use with a high speed serial link between two subsystems in a data processing system

Abstract

A data recovery circuit for use in a data processing system where plural subsystems are linked by a bit serial transmission line. The data transmitted over the bit serial transmission line is in the form of a phase encoded (PE) pulse signal. The data recovery circuit includes a time delay circuit for delaying the PE pulse signal by a three-quarter bit period. The three-quarter bit period delay signal permits the generation of a control clock signal. The control clock signal is used in sampling the PE pulse signal at three-quarter bit period points in order to generate a control signal that indicates the absence or presence of a transition at the midpoint of each bit period of the PE pulse signal. The control signal is used to generate a recovered clock signal by logically combining the control signal with the PE pulse signal and a one-half bit period delayed PE pulse signal. The control signal is also used to generate a recovered data signal by clocking the control signal into two cascaded flip-flops and logically combining the outputs of the two cascaded flip-flops.

I claim: 
     
       1. A data processing system, comprising: at least two subsystems;   a bit serial line for transmitting data between said two subsystems;   a data encoder at each subsystem for encoding the data into a signal having the form of phase encoded pulses, with a first transition at the beginning of each bit period of the phase encoded pulses, a second transition before the next bit period in order to indicate one of two data values, and a lack of the second transition before the next bit period in order to indicate the other of two data values; and   a data recovery circuit at each subsystem for receiving the phase encoded pulses from the bit serial line and decoding the phase encoded pulses to recover the data, said data recovery circuit including means for sampling the phase encoded pulses at a point after the midpoint of each bit period but before the end of that bit period and storing the sampled signal, so that the sampled signal has a transition indicating whether there is a second transition during each bit period of the phase encoded pulses;   said means for sampling including means for delaying the phase encoded pulses by a period between a one-half bit period and a bit period, so that the delayed signal has a transition occurring between the midpoint and end of each bit period of the phase encoded pulses and can be used to sample the phase encoded pulses.   
     
     
       2. The data processing system of claim 1, wherein the phase encoded pulses are in the form of a biphase-space code and wherein the sampled signal has a transition where the phase encoded pulses have no second transition during each bit period of the phase encoded pulses. 
     
     
       3. The data processing system of claim 1, wherein the second transition occurs at the midpoint of the bit period, wherein said means for delaying includes a time delay circuit for delaying the phase encoded pulses by a three-quarter bit period and wherein said means for sampling further includes: a flip-flop for storing and providing the sampled signal, said flip-flop having an input for receiving the phase encoded pulses, a clock input, and an inverted output for providing an inverted sampled signal; and   an Exclusive OR gate for receiving the three-quarter bit delayed signal from the time delay circuit and the signal at the inverted output of said flip-flop, and providing its output to the clock input of said flip-flop.   
     
     
       4. The data processing system of claim 1, wherein said means for sampling further includes half bit time delay means for delaying the phase encoded pulses by a one-half bit period time delay and wherein said data recovery circuit further includes a recovered clock generating circuit for receiving the phase encoded pulses, the sampled signal from the means for sampling, and the one-half bit period delayed signal, and in response generating a recovered clock signal from the phase encoded pulses. 
     
     
       5. The data processing system of claim 4, wherein the data recovery circuit further includes a recovered data generating circuit for generating a signal representing the data recovered from the phase encoded pulses, said recovered data generating circuit including: a first flip-flop having a data input for receiving the sampled signal, a clock input for receiving the recovered clock signal, and an output;   a second flip-flop having an input connected for receiving the signal at the output of said first flip-flop, a clock input for receiving the recovered clock signal, and an output; and   an Exclusive OR gate for receiving the signals at the output of said first and second flip-flops and providing the recovered data signal.   
     
     
       6. The data processing system of claim 4, wherein said means for sampling further includes means providing an inverted sampled signal and wherein said recovered clock generating circuit includes: means for inverting the one-half bit period delayed signal;   means for inverting the phase encoded pulses;   first logic gate means for receiving and logically combining the phase encoded pulses, the inverted one-half bit period delayed signal, and the inverted sampled signal;   second logic gate means for receiving and logically combining the inverted phase encoded pulses, the one-half bit time delay signal and the sampled signal; and   third logic gate means for receiving and logically combining the outputs of said first and second logic gate means to provide the recovered clock signal.   
     
     
       7. In a data processing system having a plurality of subsystems and a bit serial transmission line for transmitting serial data between said plurality of subsystems, the improvement comprising: encoding means at each of said stations for encoding the serial data into phase encoded pulses for transmission over said bit serial transmission line, the phase encoded pulses having at least a first transition during each bit period of the phase encoded pulses and having a second transition during each bit period to represent one of two data values; and   data recovery means at each of said stations for recovering the data from the phase encoded pulses, said data recovering means including:   means for generating a control signal having a transition for indicating the presence or absence of the second transition during each bit period of the phase encoded pulse, said means for generating including means for delaying the phase encoded pulses by a period greater than the period during each bit period after which the second transition would have occurred, means for receiving the delayed phase encoded pulses and the control signal fed back from the output of said means for generating in order to generate a control clock signal, and means for sampling the phase encoded pulses in response to the control clock signal in order to provide the control signal;   means for generating a clock signal recovered from the phase encoded pulses, including means for delaying the phase encoded pulses by one-half bit period and logic circuitry for receiving the control signal, the phase encoded pulses and the one-half bit period delayed signal, and providing in response thereto the recovered clock signal; and   means for generating a data signal recovered from the phase encoded pulses, including cascaded two-state device means for receiving the control signal and being clocked by the recovered clock signal in order to provide the recovered data signal.   
     
     
       8. The data processing system of claim 7, wherein said means for sampling includes a flip-flop having a data input for receiving the phase encoded pulses, a clock input for receiving the control clock signal, and a data output for providing the control signal. 
     
     
       9. In a data processing system having a plurality of subsystems linked by a bit serial transmission line, a data recovery system for recovering a data signal and a clock signal from a phase encoded pulse signal transmitted over the bit serial transmission line, the improvement wherein said data recovery system comprises: means for generating a three-quarter bit period time delayed phase encoded pulse signal from the phase encoded pulse signal;   means for receiving the three-quarter bit time delayed signal and generating a control clock signal having a transition at three-quarter bit period points of the phase encoded pulse signal;   means for sampling the phase encoded pulse signal at three-quarter bit period points in response to the control clock signal;   means for generating a one-half bit period time delayed phase encoded pulse signal from the phase encoded pulse signal;   means for generating a recovered clock signal from the phase encoded pulse signal by logically combining the phase encoded pulse signal, the one-half bit period time delayed signal, and the control signal; and   means for generating a recovered data signal from said phase encoded pulse signal, including cascaded flip-flop means receiving the control signal and clocked by the recovered clock signal and Exclusive OR gate means for logically combining the outputs of said cascaded flip-flop means in order to provide the recovered data signal.   
     
     
       10. In a data processing system having a plurality of closely located subsystems and a bit serial transmission line for transmitting data between each of the subsystems, the improvement comprising: a data encoder at each subsystem for encoding the data into a phase encoded pulse signal having at least one transition during each bit period, the phase encoded pulse signal having a second transition during each bit period in order to represent a first of two binary data values and a lack of the second transition in order to indicate the second of two binary data values; and   a data recovery circuit at each subsystem for receiving the phase encoded pulse signal from the bit serial transmission line and recovering the data from the phase encoded pulse signal, including means for delaying the phase encoded pulses by a period greater than the period during each bit period after which the second transition would have occurred and flip-flop means for sampling the phase encoded pulse signal in response to the delayed phase encoded pulses so that the phase encoded pulses are sampled during each period following the point at which the second transition would have occurred so that a transition at the output of said flip-flop means indicates the second transition of each bit period of the phase encoded pulse signal.   
     
     
       11. In a data recovery circuit for recovering data from a signal in the form of encoded pulses, with a first transition during each bit period of the encoded pulses, a second transition at a predetermined time after the first transition and before the next bit period in order to indicate one of two data values, and a lack of the second transition before the next bit period in order to indicate the other of two data values, the improvement comprising: sampling means for sampling the encoded pulses at a point after said predetermined time of each bit period but before the end of that bit period to provide a sampled signal having a transition indicating whether there is a second transition during each bit period of the encoded pulses;   said means for sampling including means for delaying the encoded pulses by a period greater than the period during each bit period after which the second transition would have occurred, so that the delayed signal has a transition occurring after the predetermined time of each bit period of the encoded pulses and can be used to sample the encoded pulses.