Serial-parallel-serial CCD memory system with fan out and fan in circuits

Abstract

An SPS CCD memory system is provided wherein a single tap, preferably a storage node, on an input serial or shift register is connected to the input of a plurality of parallel shift registers through a fan out circuit and the output of the plurality of parallel shift registers is connected to a single tap, preferably a storage node, on an output serial or shift register through a fan in circuit.

What is claimed is: 
     
       1. A serial-parallel-serial charge coupled device memory system comprising serial input and output sections each having a charge-carrying channel,   first and second common charge-carrying channels, and   first and second adjacent subsets of a main storage section, each of said subsets including a plurality of series registers having charge-carrying channels arranged parallel to each other, each register of said plurality of series registers having an input and an output, a fan out circuit having charge-carrying channels and a common input connected to said serial input section through said first common charge-carrying channel and a plurality of outputs connected to each input of said plurality of series registers and a fan in circuit having charge-carrying channels and a common output connected to said serial output section through said second common charge-carrying channel and a plurality of inputs connected to each output of said plurality of series registers,   said serial input and output sections each including storage nodes with a transfer gate interposed between adjacent storage nodes, the common input of said fan out circuit of said first subset being coupled to a first storage node of said serial input section and the common input of said fan out circuit of said second subset being coupled to a second storage node of said serial input section, the common output of said fan in circuit of said first subset being coupled to a first storage node of said serial output section and the common output of said fan in circuit being coupled to a second storage node of said serial output section, said first storage nodes of said serial input and output sections being interconnected by said first subset and said second storage nodes of said serial input and output sections being interconnected by said second subset and a third storage node interposed between said first and second storage nodes in each of said serial input and output sections.   
     
     
       2. A serial-parallel-serial charge coupled device memory system as set forth in claim 1 wherein the fan out circuit of each of said subsets includes three charge-carrying channels arranged between the common input and the input to three registers of said plurality of series registers and the fan in circuit of each of said subsets includes three charge-carrying channels arranged between the output of said three registers and the common output. 
     
     
       3. A serial-parallel-serial charge coupled device memory system as set forth in claim 1 wherein said serial input and output sections further include a two phase clocking system with a first pulse controlling the first and second storage nodes of said serial input section and the third storage node of said serial output section, and a second pulse controlling the first and second storage nodes of said serial output section and the third storage node of said serial input section. 
     
     
       4. A serial-parallel-serial charge coupled device memory system as set forth in claim 1 wherein said serial input and output sections and said main storage section are formed on a semiconductor substrate and wherein said fan out circuit, said fan in circuit and said plurality of series registers each includes storage nodes with a transfer gate interposed between adjacent storage nodes, the storage nodes and transfer gates of said serial input and output sections and of said main storage section include electrodes made of first and second layers of conductive material separated from said substrate by a layer of insulation. 
     
     
       5. A serial-parallel-serial charge coupled device memory system as set forth in claim 4 wherein the electrodes of said storage nodes are made from one layer of said first and second layers of conductive material and the electrodes of said transfer gates are made from the other layer of said first and second layers of conductive material. 
     
     
       6. A serial-parallel-serial charge coupled device memory system as set forth in claim 5 wherein said first and second layers of conductive material are made of polysilicon and said first layer of polysilicon is interposed between said second layer of polysilicon and said layer of insulation and wherein the electrodes of said storage nodes are made of said first layer of polysilicon and the electrodes of said transfer gates are made of said second layer of polysilicon. 
     
     
       7. A serial-parallel-serial charge coupled device memory system as set forth in claim 5 wherein the electrodes of said transfer gates overlap a portion of the electrodes of said storage nodes. 
     
     
       8. A serial-parallel-serial charge coupled device memory system as set forth in claim 7 wherein said serial input and output sections further include a first clock pulse system coupled to the electrodes of the storage nodes and transfer gates of said serial input and output sections and wherein said main storage section further includes a second clock pulse system coupled to the electrodes of the storage nodes and transfer gates of said main storage section. 
     
     
       9. A serial-parallel-serial charge coupled device memory system as set forth in claim 8 wherein said first clock pulse system is a two phase system and said second clock pulse system is an n phase system, where n is greater than two.