Power on reset circuit

Abstract

A CMOS power on reset circuit is provided which operates with low power supply voltages and yet uses a minimum amount of DC power. The circuit includes a threshold detector which provides an output when the power supply voltage exceeds the transistor threshold voltage by approximately half a volt. A capacitor is connected to the positive power supply terminal to avoid having a narrow output pulse when the power supply rises at a low rate. An output buffer/inverter can be used to provide a better output pulse and to provide a desired output polarity.

We claim: 
     
       1. A power on reset circuit coupled between a first and a second voltage node, comprising: a resistance means having a first and a second end, the first end being coupled to the first voltage node; a field effect transistor having a gate, a drain, and a source, the gate and drain being coupled to the second end of the resistance means, the source being coupled to the second voltage node; a controllable switch having an input and an output, the input being coupled to the second end of the resistance means; a capacitor coupled between the first voltage node and the output of the controllable switch; a first inverter having an input and an output, the input of the first inverter being coupled to the output of the controllable switch; and a second inverter having an input and an output, the input of the second inverter being coupled to the output of the first inverter wherein the controllable switch is a transmission gate. 
     
     
       2. The power on reset circuit of claim 1 wherein the transmission gate has a P-channel field effect transistor and an N-channel field effect transistor connected in parallel and each having a gate, the gate of the P-channel transistor being coupled to the second voltage node, and the gate of the N-channel transistor being coupled to the first voltage node. 
     
     
       3. The power on reset circuit of claim 2 wherein the first and second inverters each have a P-channel field effect transistor connected in series with an N-channel field effect transistor, each transistor having a gate coupled to the input of the respective inverter. 
     
     
       4. A power on reset circuit coupled between a first and a second voltage node, comprising: a resistance means having a first and a second end, the first end being coupled to the first voltage node; a field effect transistor having a gate, a drain, and a source, the gate and drain being coupled to the second end of the resistance means, the source being coupled to the second voltage node; a controllable switch having an input and an output, the input being coupled to the second end of the resistance means; a capacitor coupled between the first voltage node and the output of the controllable switch; a first inverter having an input and an output, the input of the first inverter being coupled to the output of the controllable switch; and a second inverter having an input and an output, the input of the second inverter being coupled to the output of the first inverter, wherein the first and second inverters each have a P-channel field effect transistor connected in series with an N-channel field effect transistor, each transistor having a gate coupled to the input of the respective inverter, and wherein the P-channel field effect transistor of the first inverter is of a larger physical size than the N-channel field effect transistor of the first inverter. 
     
     
       5. A CMOS power on reset circuit coupled between a first and a second voltage node, comprising: a threshold detector having an output; a controllable switch coupled to the output of the threshold detector and having an output; a capacitive means coupled between the output of the controllable switch and the first voltage node; and a first CMOS inverter coupled to the output of the controllable switch and providing an output which becomes a constant output voltage after a predetermined delay from the time that the threshold level has been reached. 
     
     
       6. The CMOS power on reset circuit of claim 5 further including a second CMOS inverter coupled to the output of the first CMOS inverter and providing an output pulse indicating that the power has reached the threshold level.