Linearized multiplier device for triple product convolvers

Abstract

The output signals of a number of variable transconductant multipliers areinerized so as to enable a triple product convolver to calculate Fourier transforms or produce beam forming of signals more accurately. Each of the multipliers includes a differential transistor pair, a current source and an emitter follower all properly interconnected together. The current source and emitter follower function as a linear voltage-to-current converter while differential transistor pair provides for linearity over a preestablished dynamic range. Such linearity is assured by a capacitor coupled between the emitter-base junction of the input transistor of the differential transistor pair. This capacitor has a magnitude equal to the sum of the stray circuit capacitance between the emitters of the differential transistor pair and ground plus the difference between the emitter-base capacitances of the differential transistor pair.

What is claimed is: 
     
       1. In a convolver for optionally calculating Fourier transforms or beamforming and having a delay line tapped by a plurality of variable transconductance multipliers each including a differential transistor pair an improvement therefor is provided comprising: means coupled across the emitter and base junction of the input transistor of each differential transistor pair for linearizing the impedance of each transconductive multiplier to assure an extended dynamic range of the convolver.   
     
     
       2. An improved convolver according to claim 1 in which an impedance linearizing means is coupled across the emitter and base junction of the input transistor of the differential transistor pair. 
     
     
       3. An improved convolver according to claim 2 in which the impedance linearizing means in a capacitor. 
     
     
       4. An improved convolver according to claim 3 in which the capacitor has a value equal to the stray circuit capacitance of the emitters of the differential transistor pair and ground plus the difference between the emitter base capacitance of the differential transistor pair.