Circuit for switching and transmitting alternating voltages

Abstract

A circuit for switching and transmitting alternating voltages comprise an MOS transistor, the pn-junctions which surround the source and drain regions being biased in a blocking direction in the driven condition of the transistor, correspondence between the potential difference between gate and alternating voltages and the required drive voltage of the transistor being achieved by a circuit which largely synchronizes gate voltage changes with the alternating voltage to be transmitted.

What is claimed is: 
     
       1. In a circuit for switching and transmitting alternating voltages having an MOS transistor provided with a gate and further provided with source and drain regions surrounded by pn-junctions, biassing means connected to bias both junctions in their blocking direction in the driven condition of the transistor, and circuit means connected for substantially synchronising the gate voltage changes, in the driven condition of the transistor, with the alternating voltage to be transmitted, the improvement wherein said circuit means comprise a capacitance connected between the transmission path of said MOS transistor and said gate for causing the instantaneous potential difference between the gate voltage and the alternating voltage to be transmitted to correspond to the switching voltage which is required in order to drive said transistor. 
     
     
       2. A circuit as defined to claim 1, wherein said capacitance is connected between said drain connection and said gate connection of said MOS transistor. 
     
     
       3. A circuit as defined in claim 2 further comprising a control transistor having a switchable path connected to the gate connection of said MOS transistor. 
     
     
       4. A circuit as defined in claim 3, wherein said control transistor is a second MOS transistor with a drain connection connected to the gate connection of said first-recited MOS transistor for transmitting said alternating voltage; and a further series resistor is connected between a connection of said two MOS transistors and a centre connection of a series circuit comprising said capacitance and a series resistance, connected to a d.c voltage source. 
     
     
       5. A circuit as defined in claim 1, wherein the gate connection of said MOS field-effect transistor is connected to one pole of a voltage source which delivers direct voltage to said gate via a series resistance and said capacitance between said gate connection and said source or drain connection has a value ##EQU6## where f u  is the lower limit frequency of the alternating voltage U AC  which is to be transmitted. 
     
     
       6. A circuit as defined in claim 1 wherein a direct voltage is applied to said source or drain connection of the said MOS field-effect transistor with said direct voltage being so large and so poled that said pn-junctions surrounding said source and drain regions always remain blocked for the maximum alternating voltage transmitted in ON operation of the transistor. 
     
     
       7. A circuit as defined in claim 6, wherein said direct voltage applied to said source or drain connection has the following value: ##EQU7## whereby U ACmax  is the effective value of the maximum alternating voltage to be transmitted. 
     
     
       8. A circuit as defined in claim 1 wherein said MOS field-effect transistor has a n-conducting channel.