Digital signal transmission system including means for converting asynchronous signals to the operating speed of a transmission line

Abstract

In a digital signal transmission system wherein input digital signals having an arbitrary bit rate are converted into digital signals of a bit rate higher than that of the input digital signals and then transmitted through a signal format converter; in order to realize the signal format conversion in real time the signal format converter is constructed of a buffer circuit of small capacity, a circuit which writes the input signals into the buffer circuit at the bit rate of said input signals and which reads out the written signals at the bit rate of a transmission line, a circuit which distinguishes the signals to-be-read as a mark, space and empty, and an encoding circuit which converts the mark, space and empty into pulse signals discernible with the unit being a time slot of the transmission line or integral times the time slot, in dependence of the levels of pulses or the numbers of successive pulses (run length).

We claim: 
     
       1. A digital signal transmission system wherein input digital signals are converted on a bit-by-bit basis into digital signals with a bit rate higher than that of the input digital signals by a signal format converter and then transmitted over a media having a given transmission speed, said signal format converter comprising a buffer circuit, writing means for writing the input signals into said buffer circuit at the bit rate of said input signals, reading means for reading out the written signals from said buffer circuit at a bit rate which is higher than that of said input signals and is equal to said transmission speed, and an encoder which discerns a mark and a space of the read signals and an empty representative of the non-existence of any signal to be read out and which, in case of the empty, inserts a dummy signal which is distinguishable from signals corresponding to the mark and the space by amplitude or pulse duration. 
     
     
       2. A digital signal transmission system according to claim 1, wherein said encoder includes means for adding a pulse when said buffer circuit has no signal to be read out, said pulse having a level different from those of the converted signals of the mark and the space of the signals to be transmitted. 
     
     
       3. A digital signal transmission system according to claim 1, wherein said encoder includes means for converting the read signal from said buffer circuit corresponding to said mark into a signal with a predetermined run length, means for converting the read signal corresponding to said space into a signal with another predetermined run length, and means for converting the non-existence of any signal to-be-read-out in said buffer circuit into a signal with a run length different from those of the cases of said mark and said space. 
     
     
       4. A digital signal transmission system according to claim 1, wherein said encoder includes means for converting the read signal corresponding to the mark into a signal with a run length even (or odd) times a clock period of a transmission line, means for converting the read signal corresponding to the space into a signal with a run length odd (or even) times said clock period of said transmission line, and means responsive to the nonexistence of any signal to be read out for adding a number of succession of a signal level to the converted signals of said mark and said space so as to fulfill the above conditions. 
     
     
       5. A digital signal transmission system according to claim 1, wherein there are a plurality of input signals having arbitrary bit periods; said signal format converter including a plurality of buffer circuits connected respectively to receive a respective one of said plurality of input signals, said writing means including means for writing said input signals into said buffer circuits at respective bit periods of said input signals and said reading means including means for reading the written signals out of said buffer circuits at a common reading bit period and successively in the order in which the bit periods of the respective input signals are shorter, and after reading out the signal of the longest bit period the signal of the shortest bit period is read out again, and in the nonexistence of any signal to-be-read-out a redundant signal is added and thereafter the buffer circuit corresponding to the signal of the shortest bit period is returned to and has its content read out. 
     
     
       6. A digital signal transmission system according to claim 1, wherein said encoder includes means for inserting in an empty a dummy signal which is distinguishable from the mark and the space in terms of the intervals between two adjacent pulse transients. 
     
     
       7. A digital signal transmission system according to claim 1, wherein said encoder includes means for inserting in an empty a dummy signal which is distinguishable from the mark and the space in terms of pulse amplitude. 
     
     
       8. A digital signal transmission system according to claim 1, wherein said buffer circuit includes means responsive to said reading means for providing a first output corresponding to the mark in said input signals and a second output corresponding to an empty. 
     
     
       9. A digital signal transmission system according to claim 8, wherein said encoder includes first level converter means responsive to said first output of said buffer circuit for generating a pulse at a first amplitude level, second level converter means responsive to said second output of said buffer circuit for generating a pulse at a second amplitude level, and means for combining the outputs of said first and second level converter means. 
     
     
       10. A digital signal transmission system according to claim 9, wherein said combining means is an OR gate. 
     
     
       11. A digital signal transmission system according to claim 8, wherein said encoder includes first pulse expander means responsive to said first output of said buffer circuit for generating a pulse having a first pulse duration, second pulse expander means responsive to said second output of said buffer circuit for generating a pulse having a second pulse duration, and means for combining the outputs of said first and second pulse expander means. 
     
     
       12. A digital signal transmission system according to claim 11, wherein said combining means includes a gate having first and second inverting inputs connected respective to said first and second pulse expander means and a third non-inverting input connected to said reading means, and a flip-flop having its input connected to the output of said gate. 
     
     
       13. A digital signal transmission system according to claim 11, wherein said combining means includes a first gate having first and second inverting inputs connected respectively to said first and second outputs of said buffer circuit and a third non-inverting input connected to said reading means, a second gate having first and second inverting inputs connected respectively to the outputs of said first and second pulse expander means and a third non-inverting input connected to said reading means, the output of said second gate being connected to said buffer circuit, an AND gate having one input connected to said first output of said buffer circuit and a second input connected to said reading means, an OR gate having respective inputs connected to the outputs of said first gate and said AND gate, and a flip-flop having its input connected to the output of said OR gate.