Horizontal phase detector gain control

Abstract

A vertical countdown circuit in a television receiver includes a vertical countdown counter from which a slot is decoded and compared in time with the counter reset signal. When the counter is locked by the incoming vertical synchronization pulse, the counter reset signal overlaps the slot resulting in a detection of vertical coincidence. When two such detections are made, a signal is applied to the phase detector in the horizontal phase lock loop to decrease its gain and thus the bandpass characteristic of the phase lock loop to provide high noise immunity. If, on the other hand, a predetermined number of counter reset signals are received which do not overlap the slot, then a signal is applied to the phase detector which increases the current therethrough to increase its gain and to increase the bandpass characteristic of the horizontal phase lock loop to provide better pull-in characteristics.

I claim: 
     
       1. An apparatus for altering the loop bandwidth of a horizontal phase lock loop in a television receiver by changing the gain of a phase detector within the phase lock loop, said television receiver receiving horizontal and vertical synchronization pulses and including a vertical countdown counter which is reset by a vertical countdown counter reset signal; comprising: first means for detecting coincidence between a predetermined state of said countdown counter and said vertical synchronization pulses;   second means coupled to said first means for generating a first potential when said countdown counter is synchronized with said vertical synchronization pulses and for generating a second potential when said countdown counter is not synchronized with said vertical synchronization pulses; and   switching means coupled to said second means and to said phase detector and responsive to said first and second potentials for altering the current in said phase detector to alter its gain.   
     
     
       2. An apparatus according to claim 1 wherein said first potential causes said current to assume a first value and said second potential causes said current to assume a second higher value to increase the gain of the phase detector. 
     
     
       3. An apparatus according to claim 2 wherein said second means includes: counting means for incrementing each time said countdown counter is out of synchronization with said vertical synchronization pulses;   third means coupled to said counting means for generating said second potential when said counting means reaches a predetermined state and for generating said first potential when said counting means is not in said predetermined state; and   reset means coupled to said first means and to said counting means for resetting said counting means with a reset signal when said countdown counter is synchronized with said vertical synchronization pulses.   
     
     
       4. An apparatus according to claim 3 wherein said reset means include means for detecting a predetermined number of successive occurrences of coincidence before generating said reset signal. 
     
     
       5. An apparatus according to claim 4 wherein said counting means is a three bit binary counter and wherein said predetermined number is two. 
     
     
       6. A method for altering the loop bandwidth of a horizontal phase lock loop in a television receiver by changing the gain of a phase detector within the phase lock loop, said television receiver receiving horizontal and vertical synchronization pulses and including a vertical countdown counter which is reset by a vertical countdown counter reset signal, comprising: detecting coincidence between a predetermined state of said countdown counter and said vertical synchronization pulses;   generating a first potential when said countdown counter is synchronized with said vertical synchronization pulses;   generating a second potential when said countdown counter is not synchronized with said vertical synchronization pulses; and   controlling the current in said phase detector with said first and second potential to alter its gain.   
     
     
       7. A method according to claim 6 wherein said first potential causes the current in said phase detector to assume a first value and wherein said second potential causes the current in said phase detector to assume a second higher value to increase the gain of the phase detector. 
     
     
       8. A method according to claim 7 further including: incrementing a counter each time said countdown counter is out of synchronization with said vertical synchronization pulses;   generating said second potential when said counting means reaches a predetermined state;   generating said first potential when said counting means is not in said predetermined state; and   resetting said counting means when said countdown counter is synchronized with said vertical synchronization pulses.   
     
     
       9. A method according to claim 8 including detecting a predetermined number of successive occurrences of coincidence before resetting said counting means.