Automatic gain control circuit

Abstract

An automatic gain control circuit where the direct current potential levels of the gate and the source of a field effect transistor in a preamplifier stage are maintained substantially equal during automatic gain control. In the first embodiment, the gate of the field effect transistor is responsive to a high frequency input signal and the drain provides the amplified high frequency input signals as an output signal. The source is connected to electrical ground by an inductor and is connected to a voltage source having a voltage level controlled in accordance with the automatic gain control signal. The inductor acts to shunt to ground the direct current component of the supply voltage provided to the source. In the second embodiment, the gate of the field effect transistor is responsive to a high frequency input signal and the source is connected to electrical ground. The drain is connected to a voltage source having a voltage level controlled in accordance with the automatic gain control signal and provides the amplified high frequency input signal as an output signal. The d.c. levels of the gate and source are maintained substantially equal and the AGC signal maintains a substantially zero d.c. bias on the field effect transistor to thereby minimize distortion.

What is claimed is: 
     
       1. An automatic gain control circuit comprising: (a) a preamplifier means having a field effect transistor (FET) responsive to a high frequency input signal for amplifying said high frequency input signal and for providing said amplified high frequency input signal as an output signal, said field effect transistor having a gate, source and drain, said gate being responsive to said high frequency input signal, said source being coupled to electrical ground and said output signal being provided at said drain;   (b) an automatic gain control signal source;   (c) supply voltage means for providing to said drain from a voltage source a supply voltage controlled by said automatic gain control signal; and   (d) means for biasing said field effect transistor such that said gate and said source are at substantially the same d.c. potential for all values of said automatic gain control signal.   
     
     
       2. An automatic gain control circuit as defined in claim 1, wherein said supply voltage means includes an active device connected between said voltage source and said FET drain and controlled by said automatic gain control signal for providing said supply voltage to said FET drain in accordance with said automatic gain control signal. 
     
     
       3. An automatic gain control circuit as defined in claim 2 wherein said active device of said supply voltage means is a second transistor having an emitter, a base and a collector, said emitter connected to said voltage source, said base responsive to said automatic gain control signal and said collector providing said supply voltage in accordance with said automatic gain control signal. 
     
     
       4. An automatic gain control circuit as defined in claim 3, wherein said supply voltage means further includes a first resistor and a first capacitor, said first resistor being connected between said collector of said second transistor and said drain of said field effect transistor, and said first capacitor being connected between said collector of said second transistor and electrical ground. 
     
     
       5. An automatic gain control circuit as defined in claim 1 wherein said biasing means comprises a second resistor coupled between said gate and ground and a second capacitor coupled between said gate and a source of said high frequency signal, and wherein said source is coupled directly to ground.