Time-shared, multi-phase memory accessing system having automatically updatable error logging means

Abstract

Automatically updatable error logging means incorporated in a multi-phase, bit addressable, variable field memory system. The memory system is partitioned into a plurality of individually addressable memory stacks and employs time-shared accessing of the memory stacks along with time-shared error detection and correction which is used with the error logging means to provide for automatic logging of detected errors during memory accesses on a priority basis.

What is claimed is: 
     
       1. In combination: means providing items of digital data, each having an associated check code chosen to permit the indication of a plurality of different types of data error conditions which may be present with respect to said items of data;   signal pattern generation means to which said items of data and their associated error check codes are sequentially applied, said signal pattern generating means being responsive to said data items and associated check codes to generate one of a plurality of different data error signal patterns indicating which if any of said plurality of different types of data error conditions is present with respect to each item of data; and   error log circuitry to which the data error signal patterns generated by said signal pattern generation means are applied;   said error log circuitry including first means for decoding said signal patterns and in response to said decoding providing indications of the occurrence of at least two of said different types of error conditions which may be present with respect to a plurality of data items applied to said signal pattern generation means over a predetermined time period;   said error log circuitry also including second means responsive to said signal patterns and to said indications of different types of data error conditions provided by said first means for establishing priorities between particular applied data error signal patterns and for indicating the highest priority data error signal pattern obtained for a plurality of data error signal patterns applied to said error log circuitry over said predetermined time period.   
     
     
       2. The invention in accordance with claim 1, wherein said first means of said error log circuitry includes a first register for storing said indications of different types of data error conditions produced over said predetermined time period, and wherein said second means of said error log circuitry includes a second register for storing the highest priority data error signal pattern applied over said predetermined time period. 
     
     
       3. The invention in accordance with claim 2, wherein said error log circuitry including means responsive to a signal occurring at the end of said predetermined time period for transmitting said indications of different types of data error conditions stored in said first register of said first means along with the highest priority data error signal pattern stored in said second register of said second means. 
     
     
       4. The invention in accordance with claim 3, including means for clearing said first and second registers after transmission of the contents thereof. 
     
     
       5. The invention in accordance with claim 1, 2, or 3, wherein said indications of different types of data error conditions which may be provided by said first means of said error log circuitry includes a means for providing a single digit error indication and a means for providing a multiple digit error indication. 
     
     
       6. The invention in accordance with claim 5, including means for signifying that said indications of different types of data error conditions which may be provided by said first means may indicate a plurality of the same type of data error conditions with respect to a plurality of data items applied to said signal pattern generation means over said predetermined time period. 
     
     
       7. The invention in accordance with claim 1, wherein said first means of said error log circuitry includes means capable of providing at least said two different types of indications simultaneously. 
     
     
       8. The invention in accordance with claim 1 or 2, wherein said second means of said error log circuitry includes logic circuitry for giving priority to a data error signal pattern corresponding to a first occurring error condition over that of a data error signal pattern corresponding to a later occurring error condition of the same type. 
     
     
       9. The invention in accordance with claim 8, wherein said logic circuitry of said second means gives priority to a data error signal pattern indicating a said multiple bit error over that of a said data error signal pattern indicating a single bit error. 
     
     
       10. The invention in accordance with claim 1, 2 or 3, wherein each data item is derived from a memory accompanied by an associated memory address, and wherein said second means of said error log circuitry also includes an indication of the memory address of said highest priority data error signal pattern.