Information transfer system wherein bidirectional transfer is effected utilizing unidirectional bus in conjunction with key depression signal line

Abstract

An information transfer system is described that includes a central processing unit (CPU) interconnected with a peripheral device such as an operator console by an interface bus of finite capacity. Transfer of information in the system is normally in a preferred direction from the CPU to the console. Provision is made to transfer information concerning key depressions on the console from the console to the CPU without using the bus by utilizing a normally continuously operating counter in the CPU that provides a sequence of coded count signals representative of individual keys that are provided on the console and that may be depressed. A comparator in the console compares coded count signals from the CPU counter with coded signals from the console representative of actual key depressions and provides a stop signal to the CPU counter via a single control line when an equal compare of the CPU counter and console coded signals occurs. The stopped coded count condition of the counter represents the actual key depressed. The CPU can then interrogate the current coded count state of the counter in the CPU at a convenient time to determine the actual key depressed and confirm that it has received the key depression information by operating indicators, such as visual and/or audible means in the console thus the interface bus capacity is not impacted by the transfer of the key depression information from the console to the CPU.

We claim: 
     
       1. An information transfer system, said system utilizing digital data to represent information, said digital data being represented by coded characters, said system incorporating a central processing unit having facilities for processing said digital data and for supplying digital data processor output signals indicative of status information and the like and responding to digital data input signals in said system, and said system requiring transfer of said digital data in both an output direction from said central processing unit and in an input direction to said central processing unit, said central processing unit having a processor bus for transferring digital data in said system, said system comprising: a device externally located from said central processing unit, said device being activatable to selectively provide a predetermined number of distinct digital data signals for input to said central processing unit and said device further comprising a selectively operable advisory unit, said advisory unit being responsive to digital data output signals from said central processing unit to provide advisory information;   a device data bus for receiving and transferring digital data from said central processing unit in an output direction only;   counter means incorporated in said central processing unit and operable in a count mode and a stop mode, said counter means being operable responsive to a start signal to provide a count sequence of digital data signals corresponding in number and code configuration to the predetermined number of distinct digital data input signals provided by said device, and said counter means being operable responsive to a stop signal to provide signals representative of the digital data signals that are active when said counter means is stopped;   data transfer bus means operable in a first mode for interconnecting said counter means to said device data bus for transfer of counter signals to said device and operable in a second mode for interconnecting said processor bus to said device data bus for transfer of processor output signals to said device, said data transfer bus means having bus drive means to drive said device data bus so that digital data from said counter means in said first mode and from said processor bus in said second mode is transferred via said device data bus in an output direction only from said central processing unit to said device, thereby making said device data bus unavailable for transfer of digital data in an input direction from said device to said central processing unit;   comparator means in said device, said comparator means being operable to compare the count sequence of digital data signals received from said counter means via said device data bus when said counter means is in a count mode and said data transfer bus means is in said first mode of operation and digital data signals provided by said device when activated, respectively, and said comparator means having a single input signal line interconnected from said device to said counter means in said central processng unit and said comparator means being further operable to provide an input signal via said single input signal line to change the state of said counter means from a count mode to a stop mode when digital data signals from said counter means and digital data signals from said device are identical whereby said counter means is stopped in a count state representative of a particular one of said distinct digital data signals currently activated at said device thereby accomplishing transfer of the digital data from said device in an input direction to said central processing unit by utilizing only said single input signal line and whereupon the state of said counter means and accordingly the identity of the particular one of said distinct digital data signals currently activated can be determined by said central processing unit;   advisory selection and operating means responsive to digital data signals supplied by said central processing unit via said processor bus and said device data bus when said data transfer bus means is in said second mode of operation for selectively operating said advisory unit in accordance with status information and the like from said central processing unit.   
     
     
       2. The system of claim 1 wherein said status information is representative of digital data signals provided by said device. 
     
     
       3. The system of claim 1 further comprising: device interrupt generation logic for analyzing and confirming valid entries of said keyboard signals and for providing at least one interrupt signal to said central processing unit.   
     
     
       4. An information transfer system, said system utilizing digital data to represent information, said digital data being represented by coded characters, each character comprising a predetermined plurality of binary digital signals transferred in parallel in said system, said system incorporating a central processing unit having facilities for processing said digital data and for supplying digital data processor output signals indicative of status signals and the like and responding to digital data input signals in said system, and said system requiring transfer of said digital data in both an output direction from said central processing unit and in an input direction to said central processing unit, said central processing unit having a processor bus for transferring the predetermined digital data in said system, said system comprising: a device externally located from said central processing unit, said device having an entry unit with a predetermined number of entry means for entering digital data, each of said entry means having associated entry switch means selectively settable to represent particular coded characters in said system and said entry means and associated switch means being activatable by an operator to provide digital data signals for input to said central processing unit representative of the entry means activated by said operator and said device further comprising a selectively operable advisory unit, said advisory unit being responsive to digital data output signals from said central processing unit to provide advisory information to said operator;   a device data bus for receiving and transferring digital data from said central processing unit in an output direction only;   counter means incorporated in said central processing unit and operable in a count mode and a stop mode, said counter means being operable responsive to a start signal to provide a count sequence of digital data signals corresponding in number and code configuration to said entry means in said device, and said counter means being operable responsive to a stop signal to provide signals representative of the digital data signals that are active when said counter means is stopped;   data transfer bus means operable in a first mode for interconnecting said counter means to said device data bus for transfer of counter signals to said device and operable in a second mode for interconnecting said processor bus to said device data bus for transfer of processor output signals to said device, said data transfer bus means having bus drive means to drive said device data bus so that digital data from said counter means in said first mode and from said processor bus in said second mode is transferred via said device data bus in an output direction only from said central processing unit to said device, thereby making said device data bus unavailable for transfer of digital data in an input direction from said device to said central processing unit;   entry bus means in said device including an entry bus connected to said entry unit for transmitting digital data signals within said device from said entry switch means as another source of digital data code signals;   comparator means in said device, said comparator means being operable to compare the count sequence of digital data signals received from said counter means via said device data bus when said counter means is in a count mode and said data transfer bus means is in said first mode of operation and digital data signals received from said entry switch means via said entry bus, respectively, and said comparator means having a single input signal line interconnected from said device to said counter means in said central processing unit and said comparator means being further operable to provide an input signal via said single input signal line to change the state of said counter means from a count mode to a stop mode when digital data signals from said counter means and digital data signals from said entry switch means are identical whereby said counter means is stopped in a count state representative of an entry means currently activated at said device thereby accomplishing transfer of the digital data from said entry means in said device in an input direction to said central processing unit by utilizing only said input signal line and whereupon the state of said counter means and accordingly the identity of the entry means currently activated can be determined by said central processing unit; and   advisory selection and operating means responsive to digital data signals supplied by said central processing unit via said processor bus and said device data bus when said data transfer bus means is in said second mode of operation for selectively operating said advisory unit in said device in accordance with status information from said central processing unit.   
     
     
       5. The system of claim 4 wherein said entry unit comprises a keyboard unit, said entry means comprise entry keys, and wherein said input signal device is a single key depression signal line. 
     
     
       6. The system of claim 4, further comprising: device interrupt generation logic interconnected with said counter means and a pair of counters cooperatively connected together and further including counter logic means operable to establish a first count interval and a second count interval, said pair of counters being operable during said first count interval to provide a signal to said central processing unit to indicate that the entry switch means in said entry unit is correctly activated to thereby confirm the entry of digital data signals and to serve as an interrupt signal to said central processing unit and said counters being operable during said second count interval to provide a sufficient time for said central processing unit to detect said entry of digital data signals from said entry unit.   
     
     
       7. An information transfer system, said system utilizing digital data to represent information, said digital data being represented by coded characters, each character comprising a predetermined plurality of binary digital signals transferred in parallel in said system, said system incorporating a central processing unit having facilities for processing said digital data and for supplying digital data processor output signals indicative of status signals and the like and responding to digital data input signals in said system, and said system requiring transfer of said digital data in both an output direction from said central processing unit and in an input direction to said central processing unit, said central processing unit having a processor bus for transferring the predetermined digital data in said system, said system comprising: a device externally located from said central processing unit, said device having an entry unit with a predetermined number of entry means for entering digital data, each of said entry means having associated entry switch means selectively settable to represent particular coded characters in said system and said entry means and associated switch means being activatable by an operator to provide digital data signals for input to said central processing unit representative of the entry means activated by said operator and said device further comprising a selectively operable advisory unit, said advisory unit having visual indicator means responsive to processor output signals from said central processing unit to provide advisory information to said operator and said advisory unit further having audible signal means operable in response to selected ones of said processor output signals from said central processing unit;   a device data bus for receiving and transferring digital data from said central processing unit in an output direction only;   counter means incorporated in said central processing unit and operable in a count mode and a stop mode, said counter means being operable responsive to a start signal to provide a count sequence of digital data signals corresponding in number and code configuration to said entry means in said device, and said counter means being operable responsive to a stop signal to provide signals representative of the digital data signals that are active when said counter means is stopped;   data transfer bus means operable in a first mode for interconnecting said counter means to said device data bus for transfer of counter signals to said device and operable in a second mode for interconnecting said processor bus to said device data bus for transfer of processor output signals to said device, said data transfer bus means having bus drive means to drive said device data bus so that digital data from said counter means in said first mode and from said processor bus in said second mode is transferred via said device data bus in an output direction only from said central processing unit to said device, thereby making said device data bus unavailable for transfer of digital data in an input direction from said device to said central processing unit;   entry bus means in said device including an entry bus connected to said entry unit for transmitting digital data signals within said device from said entry switch means as another source of digital data code signals;   comparator means in said device, said comparator means being operable to compare the count sequence of digital data signals received from said counter means via said device data bus when said counter means is in a count mode and said data transfer bus means is in said first mode of operation and digital data signals received from said entry switch means via said entry bus means, respectively, and said comparator means having a single input signal line interconnected from said device to said counter means in said central processing unit and said comparator means being further operable to provide an input signal via said single input signal line to change the state of said counter means from a count mode to a stop mode when digital data signals from said counter means and digital data signals from said entry switch means are identical whereby said counter means is stopped in a count state representative of an entry means currently activated at said device thereby accomplishing transfer of the digital data from said entry means in said device in an input direction to said central processing unit by utilizing only said input signal line and whereupon the state of said counter means and accordingly the identity of the entry means currently activated can be determined by said central processing unit;   interrupt generation logic interconnected with said central processing unit including an exclusive or circuit responsive to digital data signals from said device upon each activation thereof to supply a first interrupt signal to inform said central processing unit of such activation and said interrupt generation logic being further responsive to deactivation of said device and termination of said digital data signals to supply a second interrupt signal to inform said central processing unit of such deactivation; and   advisory selection and operating means operable under control of said central processing unit via said processor bus and said data transfer bus in response to said first interrupt signal from said interrupt generation logic and when said data transfer bus means is in said second mode of operation for selectively operating said visual indicators and said audible signal means in said advisory unit to convey both visual and audible indications in accordance with status information from said central processing unit, the operation of said audible signal means thereby confirming that digital data signals from said device have been received by said central processing unit, said advisory selection and operating means being further operable under control of said central processing unit in response to said second interrupt signal from said interrupt generation logic for terminating operation of said audible signal means in said advisory unit.   
     
     
       8. The system of claim 7, wherein said externally located device comprises an operator console, wherein each of said entry means has associated switch means arranged in rows and columns wherein said counter means comprises a recirculating counter and wherein comparator means has row logic and column logic correlated with the rows and columns of said switch means for comparing the count signal sequence from said counter means and the digital data signals from said switch means.