Device for reading a quantity of electric charge

Abstract

An analog device for reading a quantity of electric charge, for example, in a transversal charge transfer filter. The device includes a capacitor and two MOS transistors which are connected in series to the point in the filter where the charge is to be read. The capacitor is connected to the common point of the two transistors which are controlled in phase opposition to insure charging of the capacitor. The capacitor maintains a potential at the charge reading point constant. Any variation in the quantity of charge under an electrode is converted into a variation of potential at the common point and this forms the read signal which is detected by means of a third MOS transistor.

What is claimed is: 
     
       1. An analog device for reading a quantity of electric charge, which comprises: (a) first (Q 2  ; FIG. 1) and second (Q 3 ) transistors which are connected in series to an arrival point for said quantity of charge, said first transistor, when conducting, operating in essentially a saturation mode, said second transistor, when conducting, operating in essentially a triode mode;   (b) a first capacitor (C) having two terminals, a first one of said terminals being connected to the common point (A) of said serially connected first and second transistors, and said second terminal is connected to an external voltage source;   (c) means for supplying a d.c. potential (V DD ) from an external source to said second transistor and in series with said transistors; and   (d) means (φ 2 , φ 1 ) for alternately driving said first and second transistors (Q 2 , Q 3 ) into conduction thereby to charge said first capacitor to a potential which approaches said d.c. potential, said capacitor maintaining said arrival point (B) at a constant potential even when said quantity of charge arrives, the arrival of said quantity of charge causing a corresponding change in the potential of said common point (A), said change comprising a read signal from said device; and wherein said alternately driving means (φ 2 , φ 1 ) drives said first and second transistors into conduction for times which overlap for a quarter of a period the control signal for said second transistor.   
     
     
       2. The analog device according to claim 1, further comprising: (f) a third transistor (Q1) connected between ground and said arrival point for resetting said device to zero subsequent to a read operation, said third transistor being controlled by a signal which is in phase with the signal (QRAZ) controlling said second transistor.   
     
     
       3. The analog device according to claim 1 wherein said first and second transistors comprise MOS transistors. 
     
     
       4. The analog device according to claim 3 wherein said first and second transistors and said first capacitor are integrated on a common semi-conductor substrate. 
     
     
       5. The analog device according to claim 1 wherein the electrode of said second transistor which is not connected to said common point is connected to said external potential supply means. 
     
     
       6. The analog device according to claim 1 wherein the electrode of said second transistor which is not connected to said common point is connected to the gate electrode of the same transistor. 
     
     
       7. A charge transfer filter which comprises: (a) a semi-conductor substrate covered with an insulating layer;   (b) a plurality of electrodes on said insulating layer for controlling the charge transfer;   (c) an analog device for reading a quantity of electric charge which comprises: (1) first and second transistors which are connected in series to an arrival point for said quantity of charge, said first transistor, when conducting, operating in essentially a saturation mode, said second transistor, when conducting, operating in essentially a triode mode;   (2) a first capacitor having two terminals, a first one of said terminals being connected to the common point of said serially connected first and second transistors, and the other being connected to an external voltage source;   (3) means for supplying a d.c. potential from an external source to said second transistor and in series with said transistors;   (4) means for alternately driving said first and second transistors into conduction for times which overlap for a quarter of a period the control signal for said second transistor thereby to charge said first capacitor to a potential which approaches said d.c. potential, said capacitor maintaining said arrival point at a constant potential even when said quantity of charge arrives, the arrival of said quantity of charge causing a corresponding change in the potential of said common point, said change comprising a read signal from said device, and     (d) a second capacitor connected to said arrival point for storing said charge, said second capacitor being formed by said substrate, said insulating layer and one electrode from said electrodes where reading occurs.   
     
     
       8. An analog device for reading a quantity of electric charge, which comprises: (a) first (Q 2  ; FIG. 1) and second (Q 3 ) transistors which are connected in series to an arrival point for said quantity of charge, said first transistor, when conducting, operating in essentially a saturation mode, said second transistor, when conducting, operating in essentially a triode mode;   (b) a first capacitor (C) having two terminals, a first one of said terminals being connected to the common point (A) of said serially connected first and second transistors;   (c) means for supplying a d.c. potential (V DD ) from an external source to said second transistor and in series with said transistors;   (d) means for alternately driving said first and second transistors into conduction thereby to charge said first capacitor to a potential which approaches said d.c. potential, said capacitor maintaining said arrival point at a constant potential even when said quantity of charge arrives, the arrival of said quantity of charge causing a corresponding change in the potential of said common point, said change comprising a read signal from said device;   (e) a second capacitor connected to said arrival point to store said quantity of charge;   (f) a third transistor (Q 1 ) connected between ground and said arrival point, for resetting said device to zero subsequent to a read operation, said third transistor being controlled by a signal (φ RAZ ) which is in phase with the signal controlling second transistor; and   (g) a fourth transistor (Q 5 ) connected to said arrival point for charging said second capacitor to a predetermined value prior to the arrival of said quantity of charge, said fourth transistor being controlled by a signal (φ CH ) which is in phase opposition to the signal controlling said third transistor, the control signals for said third and fourth transistors having the same pulse width, said pulse width being equal to half the pulse width of the control signal for said second transistor.