Method of fabricating a misaligned, composite electrical contact on a semiconductor substrate

Abstract

Disclosed is a method of fabricating an electrical contact to a region which lies at the surface of a semiconductor substrate and is doped opposite thereto. The method includes the steps of forming the combination of a silicide of a noble metal at the surface of the region, a layer of a barrier metal over the silicide, and a patterned conductor on a portion of the barrier metal layer which partly covers the region; etching partway through the portion of the barrier metal which is not covered by the patterned conductor; and thereafter oxidizing to completion, the portion of the barrier metal layer which is not covered by the patterned conductor and which remains after the etching step.

What is claimed is: 
     
       1. A method of fabricating an electrical contact to a region which lies at the surface of a semiconductor substrate and is exposed through an opening in an insulating layer that overlies said surface; said method including the steps of: forming the combination of a silicide of a noble metal throughout the exposed surface of said region, a layer of a barrier metal over said silicide and said insulating layer, and a patterned conductor on a portion of said barrier metal layer; said patterned conductor being in misalignment with said opening such that it covers only part of said silicide and an adjacent portion of said insulating layer;   etching partway through the portion of said barrier metal layer which is not covered by said patterned conductor; and thereafter   oxidizing the portion of said barrier metal layer which is not covered by said patterned conductor and which remains after said etching step.   
     
     
       2. A method according to claim 1 wherein said region is doped N-type and said substrate is P-type. 
     
     
       3. A method according to claim 1 wherein said region is doped P-type and said substrate is N-type. 
     
     
       4. A method according to claim 1 wherein said barrier metal layer as formed is at least 1000 A thick, and is reduced to less than 600 A by said etching step. 
     
     
       5. A method according to claim 1 wherein said etching step is performed by a wet chemical etch. 
     
     
       6. A method according to claim 1 wherein said etching step is performed by a plasma etch. 
     
     
       7. A method according to claim 1 wherein said noble metal is platinum. 
     
     
       8. A method according to claim 1 wherein said barrier metal is titanium-tungsten. 
     
     
       9. A method according to claim 1 wherein said conductor is aluminum. 
     
     
       10. In a method of fabricating an electrical contact to a region which lies at the surface of a semiconductor substrate and is exposed through a rectangular opening in an insulating layer that overlies said surface; the improvement comprising the steps of forming a silicide of a noble metal throughout the exposed surface of said region; thereafter forming a layer of a barrier metal over said silicide and said insulating layer; thereafter forming a patterned conductor on a portion of said barrier metal layer, said patterned conductor being of substantially the same width as said opening and in misalignment with it as to cover only part of said exposed region and an adjacent portion of said insulating layer; and thereafter oxidizing at least a portion of said barrier metal layer which is not covered by said patterned conductor. 
     
     
       11. The invention of claim 10, and further including the steps of etching partway through the portion of said barrier metal layer which is not covered by said patterned conductor prior to said oxidizing step. 
     
     
       12. The invention according to claim 10 wherein said width of said opening and said patterned conductor equals the minimal dimension that can be made by method of fabricating.