Shift register-latch circuit driven by clocks with half cycle phase deviation and usable with a serial alu

Abstract

In a multiple stage data transfer circuit, suitable for transferring a plurality of bits to or from a bit processor or 1-bit arithmetic logic unit, each bit stage includes a shift register portion and a latch portion. Each shift register(S/R) portion is constructed of a series circuit consisting of a static (input) inverter, a switching element, and a dynamic (output) inverter. Each latch portion is constructed of a closed loop consisting of a static inverter, a switching element, and a dynamic inverter. Each bit stage also includes a data transfer switch element, which may be activated through an externally connected control line. The data transfer switch is coupled beween the data output terminal of the S/R switch and the data output terminal of the latch switch. The S/R and latch portion switches are activated by two different clocks, with a phase deviation therebetween of one-half cycle. When the S/R switch and data transfer switch are both "ON", data may flow from the S/R's input inverter to the latch. When the latch switch and the data transfer switch are both "ON", data may flow from the latch to the S/R's output inverter.

What is claimed is: 
     
       1. A shift register with a latch circuit comprising: a shift register which is constructed of a plurality of bit stages connected in cascade, each bit stage being formed of a series circuit consisting of a first static inverter, a first switching element and a first dynamic inverter;   a plurality of latch circuit portions which constitute the latch circuit, which correspond to the bit stages of said shift register respectively, and each of which is formed of a closed loop consisting of a second static inverter, a second switching element and a second dynamic inverter;   a plurality of third switching elements, each connected between a respective one of said bit stages of said shift register and a latch circuit portion corresponding thereto, so as to control data transfers between said shift register and said latch circuit; and   clock means connected to said shift register and said latch circuit for generating clock pulses to drive said shift register and said latch circuit so that they may shift data with a phase deviation of a half cycle therebetween.   
     
     
       2. A shift register with a latch circuit as defined in claim 1, wherein said each third switching element is connected between a signal line coupling the first switching element and the first dynamic inverter and a signal line coupling the second switching element and the second dynamic inverter. 
     
     
       3. A shift register with a latch circuit as defined in claim 1 or 2, wherein said clock means includes means for generating a first train of pulses for driving the respective first switching elements and a second train of pulses for driving the respective second switching elements, with the phase deviation of a half cycle therebetween, said respective third switching elements being connected to be driven by a signal synchronous with said first train of pulses at the data transfers from said shift register to said latch circuit and by a signal synchronous with said second train of pulses at the data transfers from said latch circuit to said shift register. 
     
     
       4. A shift register with a latch circuit as defined in claim 1, 2 or 3, further comprising fifth means connected to each latch circuit portion for selectively reading-out data from said second static inverter onto an external data line or for writing data on said data line into said second static inverter in response to an applied command signal. 
     
     
       5. In a serial arithmetic logic unit having: shift register means which is composed of a plurality of bit stages for successively shifting data from a most significant bit side thereof to a least significant bit side thereof,   1-bit arithmetic logic means connected to receive an output signal of the least significant bit stage of said shift register means and to feed a processed result back to the most significant bit stage of said shift register,   latch circuit means connected in parallel with the respective bit stages of said shift register means through a plurality of switches for temporarily storing data of a plurality of bits, and   pulse generating means for applying driving pulses to said shift register means, said 1-bit arithmetic logic means and said latch circuit means;   the improvement comprising:   each bit stage of said shift register means being formed of a series circuit which consists of a first static inverter, a first switching element and a first dynamic inverter,   said latch circuit includes a plurality of closed loops each corresponding to a respective one of the bit stages of said shift register means, each closed loop consisting of a second static inverter, a second switching element and a second dynamic inverter and being connected to the corresponding one of the bit stages of said shift register through a corresponding one of the first-mentioned switches, and   the respective first switching elements of said shift register means and the respective second switching elements of said latch circuit means being drive at operation timings with a phase deviation of a half cycle therebetween by the driving pulses applied thereto from said pulse generating means.   
     
     
       6. A shift register with a latch circuit comprising: shift register means including a plurality of bit stages connected in cascade, each bit stage including a first portion connected to an output of a preceding bit stage and a second portion connected to an output of said first portion, wherein said first portion includes means responsive to a first clock for providing a first signal having an inverted level of a signal provided from said preceding stage when the first clock is applied thereto, and said second portion including means responsive to a second clock for providing a second signal having an inverted level of a signal provided to an input thereof when the second clock is applied thereto;   latch circuit means including a plurality of latch stages, each latch stage being connected to a corresponding one of said bit stages of said shift register means and including a third portion and a fourth portion having an input and an output respectively connected to an output and an input of said third portion, wherein said third portion includes means responsive to said first clock for providing a third signal having an inverted level of a signal provided to said input thereof when the first clock is applied thereto, and said fourth portion includes means responsive to said second clock for providing a fourth signal having an inverted level of a signal provided to said input thereof;   a plurality of switch means each interposed between said output of said third portion of one of said latch stages and said output of said first portion of a corresponding one of said bit stages; and   means for rendering said switch means conductive in response to said first and second clocks, respectively, when signals are transferred from said shift register means to said latch circuit means and vice versa.   
     
     
       7. A combination according to claim 6, wherein said first portion of each bit stage comprises a first static inverter connected to the output of said preceding bit stage, and a first switch connecting an output of said first static inverter to said second portion of said each bit stage in response to said first clock; wherein said second portion of said each bit stage comprises a first dynamic inverter;   wherein said third portion of each latch stage comprises a second dynamic inverter;   wherein said fourth portion of said each latch stage comprises a second static inverter connected to receive an output of said second dynamic inverter and a second switch connecting an output of said second static inverter to said input of said third portion of said each latch stage in response to said second clock.   
     
     
       8. A combination according to claim 7, wherein each latch stage further comprises a third static inverter; a third switch connecting said output of said second static inverter to an input of said third static inverter;   a fourth switch connecting an output of said third static inverter to a data bus in response to a read signal which is provided thereto in synchronism with said first clock when a signal is to be transferred from said latch circuit means to said data bus;   a fifth switch connecting said data bus to said input of said second static inverter in response to a write signal which is provided thereto in synchronism with said second clock when a signal is to be transferred from said data bus to said latch circuit means.   
     
     
       9. A combination according to claim 6, wherein said first and second clocks are separated in time from each other by half of the cycle of said first clock.