Semiconductor strain gauge

Abstract

A semiconductor strain gauge is arranged as a bridge having four piezoresistive elements which each include a low impurity concentration diffused portion and a heavily-doped diffused portion. The resistance values of the two low impurity concentration diffused portions opposite each other in the bridge are greater than the resistance values of the other two lower impurity concentration portions. The resistances of the heavily-doped diffused portion are selected so that the resistance of the piezoresistive elements are equal. However, by virtue of the fact that the resistance temperature coefficient of the low impurity portions are greater than the resistance temperature coefficients of the high impurity portions, the overall resistance temperature coefficients of the bridge arms will be different. This permits the zero-point voltage of the bridge to always increase with an increase in temperature.

We claim: 
     
       1. A semiconductor strain gauge comprising: a semiconductor substrate of one conductivity on which a pressure sensitive diagram is formed; and   at least two piezoresistive elements formed in a major surface of said semiconductive substrate adjacent to said pressure sensitive diaphragm and having an opposite conductivity to said one conductivity,   wherein each of said piezoresistive elements includes at least one low impurity concentration diffused portion and at least one heavily-doped diffused portion connected in series, said low impurity concentration portion having a higher resistance temperature coefficient than that of the heavily-doped portion, and further wherein the resistance for each of the respective diffused portions of the piezoresistive elements is set to provide a resistance value of one low impurity concentration diffused portion in one of said piezoresistive elements higher than that of a low impurity concentration diffused portion in the other of said piezoresistive elements and a resistance value of one heavily-doped diffused portion in said one of said piezoresistive elements smaller than that of a heavily-doped diffused portion in said other of said piezoresistive elements, so that said two piezoresistive elements are substantially equal in their overall resistance but unequal in their overall resistance temperature coefficient, with the overall resistance temperature coefficient of said one piezoresistive element being greater than the overall resistance temperature coefficient of said other piezoresistive element.   
     
     
       2. A semiconductor strain gauge according to claim 1, wherein four of said piezoelectric elements are formed in said major surface of said semiconductor substrate adjacent to said pressure sensitive diaphragm, said four elements being coupled together to form an electrical bridge circuit with first, second, third and fourth arms, each having one of said elements, said first and third arms being opposite to one another and said second and fourth arms being opposite to one another and further wherein the resistance of the respective diffused portions of each of said elements in said four arms is set so that all of the arms will have a substantially equal resistance, but the resistance temperature coefficient of said first and third arms will be greater than the resistance temperature coefficient of said second and fourth arms. 
     
     
       3. A semiconductor strain gauge according to claim 1, wherein said one piezoresistive element comprises a U-shaped element having a pair of said low impurity portions coupled together by a highly-doped portion, and wherein said other piezoresistive element comprises a U-shaped element having a pair of said highly-doped portions coupled together by a low impurity portion. 
     
     
       4. A semiconductor strain gauge according to claim 2, wherein the piezoresistive elements of said first and third arms comprise U-shaped elements having a pair of said low impurity portions coupled together by a highly-doped portion, and wherein the piezoresistive elements of said second and fourth arms comprise U-shaped elements having a pair of highly-diffused portions coupled together by a low impurity portion. 
     
     
       5. A semiconductor strain gauge for coupling to a zero-point compensation circuit comprising: a semiconductor substrate of one conductivity, on which a pressure sensitive diaphragm is formed; and   at least two piezoresistive elements formed in a major surface of said semiconductive substrate adjacent to said pressure sensitive diaphragm and having an opposite conductivity to said one conductivity,   wherein each of said piezoresistive elements includes at least one low impurity concentration diffused portion and at least one heavily-doped diffused portion connected in series, said low impurity concentration portion having a higher resistance temperature coefficient than that of the heavily-doped portion, and further wherein the resistance for each of the respective diffused portions of the piezoresistive elements is set to provide a resistance value of one low impurity concentration diffused portion in one of said piezoresistive elements higher than that of a low impurity concentration diffused portion in the other of said piezoresistive elements and a resistance value of one heavily-doped diffused portion in said one of said piezoresistive elements smaller than that of a heavily-doped diffused portion in said other of said piezoresistive elements, so that said two piezoresistive elements are substantially equal in their resistance but unequal in their overall resistance temperature coefficient, with the overall resistance temperature coefficient of said one piezoresistive element being greater than the overall temperature coefficient of said other piezoresistive element so that a zero-point output voltage of said strain gauge which will be fed to said zero-point compensation circuit will always increase with a rise in temperature.   
     
     
       6. A semiconductor strain gauge according to claim 5, wherein four of said piezoelectric elements are formed in said major surface of said semiconductor substrate adjacent to said pressure sensitive diaphram, said four elements being coupled together to form an electrical bridge circuit with first, second, third and fourth arms, each having one of said elements, said first and third arms being opposite to one another and said second and fourth arms being opposite to one another and further wherein the resistance of the respective diffused portions of each of said elements in said four arms is set so that all of the arms will have a substantially equal resistance, but the resistance temperature coefficient of said first and third arms will be greater than the resistance temperature coefficient of said second and fourth arms.