Filter circuit having a charge transfer device

Abstract

A filter circuit comprising a charge transfer device of the type which includes first and second sets of charge storage devices, such as capacitors, the first and second sets of charge storage devices being supplied with first and second clock signals, respectively, and further including first and second sets of switches which are actuated in response to the first and second clock signals, respectively, each switch being operable, when actuated, to transfer charge between a charge storage device in one set and a charge storage device in the other set, thereby transferring a charge through succeeding switches to be temporarily stored in succeeding charge storage devices. A semiconductor element, such as a transistor, is actuated in response either to the first or to the second clock signals for transferring the charge stored in a first predetermined charge storage device to a second predetermined charge storage device. An output circuit is coupled to a preselected charge storage device for deriving an output signal from the filter circuit.

What is claimed is: 
     
       1. A filter circuit comprising charge transfer means, including first and second sets of charge storage means, said first set of charge storage means being supplied with a first clock signal and said second set of charge storage means being supplied with a second clock signal, first and second sets of switch means, said first set of switch means being actuated in response to said first clock signal and said second set of switch means being actuated in response to said second clock signal, respective ones of said switch means in said first set being operable when actuated to transfer charge between a charge storage means in said first set and a charge storage means in said second set and respective ones of said switch means in said second set being operable when actuated to transfer charge between a charge storage means in said second set and a charge storage means in said first set, and means for supplying said first and second clock signals to said first and second sets of charge storage means, respectively, and to said first and second sets of switch means, respectively, thereby transferring a charge through succeeding switch means to be temporarily stored in succeeding charge storage means; means for supplying an input signal to a predetermined one of said charge storage means; semiconductor means actuated in response to a selected one of said first or second clock signals for transferring the charge stored in a predetermined first charge storage means to a predetermined second charge storage means, said predetermined first charge storage means and said predetermined second charge storage means being selected from any of said first and second sets of charge storage means; and output means coupled to a preselected charge storage means, which is selected from said first and second sets of charge storage means, for deriving an output signal from said filter circuit. 
     
     
       2. The filter circuit of claim 1 wherein each of said charge storage means comprises a capacitor, the capacitors of said first set having respective first electrodes coupled in common to receive said first clock signals and also having respective signal electrodes, and the capacitors of said second set having respective first electrodes coupled in common to receive said second clock signals and also having respective signal electrodes; and wherein each of said switch means is interconnected between the signal electrodes of two capacitors of different sets. 
     
     
       3. The filter circuit of claim 2 wherein each of said switch means comprises transistor means having its collector-emitter circuit coupled between said signal electrodes of two capacitors of different sets, the transistor means of said first set having respective base electrodes coupled in common to receive said first clock signals, and the transistor means of said second set having respective base electrodes coupled in common to receive said second clock signals. 
     
     
       4. The filter circuit of claim 3 wherein a respective capacitor of said first set is connected between the base and collector electrodes of a respective transistor means of said first set; and a respective capacitor of said second set is connected between the base and collector electrodes of a respective transistor means of said second set. 
     
     
       5. The filter circuit of claim 3 wherein said first and second clock signals are 180° out-of-phase with each other. 
     
     
       6. The filter circuit of claim 1 wherein said semiconductor means comprises transistor means having its collector-emitter circuit connected between said predetermined first and second charge storage means, and its base electrode connected to receive said selected clock signal. 
     
     
       7. The filter circuit of claim 6 wherein said transistor means has its emitter electrode connected to said predetermined first charge storage means and its collector electrode connected to said predetermined second charge storage means, the latter being supplied with the same clock signal as said transistor means. 
     
     
       8. The filter circuit of claim 7 wherein said transistor means transfers charge from said predetermined first charge storage means to said predetermined second charge storage means, the latter being in succeeding relationship to the former charge storage means. 
     
     
       9. The filter circuit of claim 8, further comprising a current mirror circuit for injecting charge into said predetermined second charge storage means from the immediately preceding switch means which transfers that charge. 
     
     
       10. The filter circuit of claim 9, further comprising additional charge transfer means supplied with the DC component of said input signal, said additional charge transfer means being coupled to said second charge storage means. 
     
     
       11. The filter circuit of claim 7 wherein said switch means comprise transistor switches, the emitter of one of said transistor switches being coupled to said predetermined first charge storage means and the base of said one transistor switch being supplied with the same clock signal as said transistor means. 
     
     
       12. The filter circuit of claim 11 wherein said transistor means and said one transistor switch exhibit balanced operation such that the emitter currents thereof exhibit a predetermined ratio. 
     
     
       13. The filter circuit of claim 12 wherein said transistor means and said one transistor switch are coupled to respective emitter resistances. 
     
     
       14. The filter circuit of claim 7, further comprising plural transistor means, some of said plural transistor means having their collector electrodes coupled in common to said predetermined second charge storage means; a current mirror circuit; others of said plural transistor means having their collector electrodes coupled in common through said current mirror circuit to said predetermined second charge storage means; each of said transistor means having its emitter electrode coupled to a respective, predetermined first charge storage means and its base electrode connected in common to receive said selected clock signal. 
     
     
       15. The filter circuit of claim 14 wherein said predetermined second charge storage means is in succeeding relationship to each of said predetermined first charge storage means. 
     
     
       16. The filter circuit of claim 14 wherein said predetermined second charge storage means is in preceding relationship to each of said predetermined first charge storage means. 
     
     
       17. The filter circuit of claim 7 wherein said transistor means transfers charge from said predetermined first charge storage means to said predetermined second charge storage means, the latter being in preceding relationship to the former charge storage means. 
     
     
       18. The filter circuit of claim 6, wherein said transistor means comprises first and second transistors having their collector-emitter circuits connected in series; said first transistor having its base electrode connected to receive one of said clock signals and said second transistor having its base electrode connected to receive the other of said clock signals. 
     
     
       19. The filter circuit of claim 18, further comprising an additional charge storage means coupled to the junction defined by said first and second transistors and connected to be supplied with said one clock signal. 
     
     
       20. The filter circuit of claim 19 further comprising a current mirror circuit; the series-connected collector-emitter circuits of said first and second transistors being coupled to said predetermined second charge storage means through said current mirror circuit. 
     
     
       21. The filter circuit of claim 20 wherein the emitter electrode of said first transistor is coupled to said predetermined first charge storage means and the collector electrode of said second transistor is coupled to said current mirror circuit. 
     
     
       22. The filter circuit of claim 20 wherein said switch means comprise transistor switches, the emitter electrode of one of said transistor switches being coupled to said predetermined first charge storage means, the base electrode of said one transistor switch being supplied with said one clock signal, and the collector electrode of said one transistor switch being connected to an immediately succeeding charge storage means; said additional and immediately succeeding charge storage means having substantially equal charge storage capacities. 
     
     
       23. The filter circuit of claim 7, further comprising means for supplying a control signal to said transistor means to control the filter characteristics of said filter. 
     
     
       24. The filter circuit of claim 23, wherein said control signal is supplied to said base electrode of said transistor means in superimposition with said selected clock signal. 
     
     
       25. The filter circuit of claim 24, wherein said predetermined second charge storage means is in succeeding relationship to said predetermined first charge storage means. 
     
     
       26. The filter circuit of claim 24, wherein said predetermined second charge storage means is in preceding relationship to said predetermined first charge storage means. 
     
     
       27. The filter circuit of claim 24 wherein said means for supplying a control signal comprises differential amplifier means connected to receive said selected clock signal and said control signal, said differential amplifier means having an output coupled to said base electrode of said transistor means. 
     
     
       28. The filter circuit of claim 27 wherein said differential amplifier means comprises a first pair of differentially-connected transistors supplied with said selected clock signal; a second pair of differentially-connected transistors supplied with said control signal thereacross, the collector-emitter circuits of respective ones of said first pair of differentially-connected transistors being connected in series with the collector-emitter circuits of respective ones of said second pair of differentially-connected transistors; constant current means connected to the collector-emitter circuits of said first and second pairs of differentially-connected transistors; and an output coupled to the collector circuit of one of said second pair of differentially-connected transistors. 
     
     
       29. The filter circuit of claim 28 wherein said switch means comprise transistor switches, the emitter electrode of one of said transistor switches being coupled to said predetermined first charge storage means, the collector electrode of said one transistor switch being connected to an immediately succeeding charge storage means, and the base electrode of said one transistor switch being coupled to the collector circuit of the other of said second pair of differentially-connected transistors. 
     
     
       30. A filter circuit comprising charge transfer means including plural stages of capacitance means for storing charge, plural transistor switches, each transistor switch interconnecting the capacitance means of one stage to the capacitance means of a succeeding stage such that, when a transistor switch is conductive, a signal charge is transferred through the collector-emitter circuit thereof from one stage to the next succeeding stage, means for supplying first clock signals to alternate ones of said transistor switches to actuate same and second clock signals to the remaining transistor switches to actuate the latter, means for supplying an input signal to an input stage and means for deriving an output signal from an output stage; charge transfer transistor means having a collector-emitter circuit interconnected between at least a first stage and a second stage to transfer charge therebetween when actuated; and means for supplying a selected one of said clock signals to said charge transfer transistor means to actuate the same. 
     
     
       31. The filter circuit of claim 30 wherein said charge transfer transistor means transfers charge from said first stage to said second stage, the latter being a succeeding stage relative to said first stage. 
     
     
       32. The filter circuit of claim 30 wherein said charge transfer transistor means transfers charge from said first stage to said second stage, the latter being a preceding stage relative to said first stage. 
     
     
       33. The filter circuit of claim 30, further comprising means interconnected between said second stage and the transistor switch which transfers signal charge thereto for inverting and injecting said signal charge to said second stage. 
     
     
       34. The filter circuit of claim 33 wherein said last-mentioned means comprises a current mirror circuit. 
     
     
       35. The filter circuit of claim 30 wherein said charge transfer transistor means comprises plural charge transfer transistors, each connected to a respective stage and to said second stage, all of said charge transfer transistors being actuated simultaneously to transfer charge from said respective stage to said second stage. 
     
     
       36. The filter circuit of claim 35, further comprising means for inverting and injecting the charge transferred by some of said charge transfer transistors to said second stage. 
     
     
       37. The filter circuit of claim 36 wherein said last-mentioned means comprises a current mirror circuit having an input coupled in common to the collector-emitter circuit of said some charge transfer transistors and an output coupled to said second stage; and wherein the collector-emitter circuits of the remaining ones of said charge transfer transistors are coupled to said second stage. 
     
     
       38. The filter circuit of claim 30 wherein said charge transfer transistor means comprises plural charge transfer transistors having their collector-emitter circuits connected in series, one of said charge transfer transistors being supplied with said first clock signal and another of said charge transfer transistors being supplied with said second clock signal; and an additional capacitance means coupled to one of said charge transfer transistors to receive at least a portion of the signal charge from said first stage, which portion is transferred thereto by said one charge transfer transistor. 
     
     
       39. The filter circuit of claim 38 further comprising means for inverting and injecting the charge transferred to said second stage by said plural charge transfer transistors. 
     
     
       40. The filter circuit of claim 39 wherein said last-mentioned means comprises a current mirror circuit. 
     
     
       41. The filter circuit of claim 30 further comprising means for supplying a control voltage to said charge transfer transistor means for controlling the charge transferred to said second stage. 
     
     
       42. The filter circuit of claim 41 wherein said means for supplying a control voltage comprises differential amplifier means supplied with said selected clock signals and with said control voltage to superimpose said selected clock signals on said control voltage and to supply same to a control electrode of said charge transfer transistor means. 
     
     
       43. The filter circuit of claim 42 wherein said differential amplifier means also is coupled to the transistor switch which transfers charge from said first stage to the next succeeding stage to control the actuation thereof.