Multi-layer passivant system

Abstract

There is disclosed a semiconductor device having a PN junction terminating at a surface and passivated by a multi-layer passivant system comprising a first layer of semi-insulating material over the surface, a layer of dielectric material over the first layer and a second layer of semi-insulating material over the dielectric layer. Preferably, the first and second layers are oxygen doped polycrystalline silicon and the dielectric layer is either silicon dioxide of frit glass fused to the first layer.

I claim: 
     
       1. A semiconductor device comprising a body of semiconductor material having at least two regions of opposite conductivity type forming a PN junction therebetween, said PN junction terminating in a surface of said body, a first layer of semi-insulating material over said surface and covering said PN junction, a layer of dielectric material over said first semi-insulating layer and a second layer of semi-insulating material over said dielectric layer. 
     
     
       2. A semiconductor device in accordance with claim 1 wherein said first and second layers of semi-insulating material comprise oxygen doped polycrystalline silicon. 
     
     
       3. A semiconductor device in accordance with claims 1 or 2 wherein said dielectric layer comprises a frit glass fused over said first semi-insulating layer. 
     
     
       4. A semiconductor device in accordance with claim 1 wherein said second semi-insulating layer extends across the surface depletion region of said junction when said junction is biased at its reverse breakdown voltage. 
     
     
       5. A semiconductor device in accordance with claim 4 wherein the outer edge of said second semi-insulating layer is spaced inwardly from the outer edge of said dielectric layer. 
     
     
       6. A semiconductor device in accordance with claim 1 wherein the resistivity of said first semi-insulating layer is such that the junction leakage current through it is about equal to or less than the reverse bias junction leakage current. 
     
     
       7. A semiconductor device in accordance with claim 1 wherein the resistivity of said first and second semi-insulating layers is from about 10 7  ohm-cm to about 10 10  ohm-cm. 
     
     
       8. A semiconductor device in accordance with claims 1 or 2 wherein the breakdown field strength of the first and second semi-insulating layers is such that it will not breakdown before said junction under reverse bias. 
     
     
       9. A semiconductor device in accordance with claim 1 wherein said dielectric layer is of a material and thickness to support about one-half the breakdown voltage of said junction. 
     
     
       10. A semiconductor device in accordance with claims 1 or 2 wherein said dielectric layer comprises silicon dioxide.