Apparatus for detecting single event

Abstract

A plurality of input signals are applied to input terminals of first and second priority encoders according to the order of priority in ascending and descending orders, respectively. The encoded output signals of the first and second priority encoders are exclusive-ORed for each corresponding pair of significant bits. A single event detection is executed only if exclusive OR is effected for all the corresponding pairs of significant bits.

What we claim is: 
     
       1. A logic circuit comprising a first priority encoder satisfying a condition 2 m-1  <n≦2 m  for n binary logic input signals and having a plurality of input terminals to which said n binary logic input signals are applied according to input priority orders i (i=0 to 2 m  -1) respectively, whereby an input signal corresponding to the highest priority is converted into a binary code signal constituted by a plurality of significant bits; a second priority encoder satisfying the same condition of said first priority encoder and having a plurality of input terminals to which said binary logic input signals are applied according to priority orders 2 m  1-i respectively, whereby an input signal corresponding to the highest priority is converted into a binary code signal constituted by a plurality of significant bits; and a gate circuit section for bitwise comparison of the binary code signals from said first and second priority encoders and for producing an output signal only when the contents of every corresponding pair of significant bits differ from each other thereby detecting a single event of the n binary logic signals on the input lines. 
     
     
       2. A logic circuit according to claim 1, characterized in that said gate circuit section is composed of gate circuit (13, 14, 15) to carry out exclusive OR operation of the corresponding significant bits of said binary code signals, and a gate circuit (16) to carry out AND operation of the exclusive OR outputs of all the corresponding significant bits. 
     
     
       3. A logic circuit according to claim 1 or 2, characterized in that if said binary logic input signals (S 0  to S n-1 ) are fewer than the input terminals of each of said first and second priority encoders (21 and 22), the same logic signals (0) are applied to remaining input terminals. 
     
     
       4. An apparatus for detecting input lines, comprising: n number of input lines supplied with binary logic signals;   a pair of priority encoders, one of which has a plurality of input terminals connected to the n number of input lines in a first order of priority and the other of which has a plurality of input terminals connected to said n number of input lines in a reverse order to the first order of priority, for encoding the binary logic signal on an input line having a logic signal nearest to one of least significant bit and most significant bit into n bit signals where 2 m-1  <n≦2 m , thereby respectively producing two sets of m bit signals; and   an exclusive logic circuit for outputting an exclusive ORed signal of said two sets m bit signals, thereby detecting input lines having logic signals thereon.