Semiconductor memory core program control circuit

Abstract

A circuit to restrain the rise time of a programming pulse generated in an electrically alterable read-only semiconductor memory in which excessively sudden changes in the pulse are capacitively coupled, through active devices that can be built on the chip, to a grounding switch device so as to periodically drain away the control signal used to create the pulse.

I claim: 
     
       1. A control circuit for regulating the programming pulse presented to the core of an electrically alterable read-only semiconductor memory, said memory being of the type in which a selected bit is read by introducing a low voltage on a program line from a low voltage supply and said selected bit is programmed by introducing a high voltage on the same program line from a high voltage supply, said control circuit being formed on the semiconductor chip and comprising: a first circuit node electrically coupled to the program line;   first switching means connected to said first node and adapted for connection to said low voltage supply, operable in response to the reception of a first input signal to connect said first node to the low voltage supply and in response to a second input signal to disconnect said first node from said low supply;   a second circuit node;   second switching means connected to said first node and adapted for connection to said high voltage supply and also controllably coupled to said second node, operable in response to the voltage at said second node to increase the voltage at said first node toward the high voltage of said high voltage supply and thereby produce said programming pulse;   a voltage increasing means connected to said second node, operable in response to the reception of said first input signal to hold said second node at a voltage such that said second switching means does not change the first node voltage and operable in response to the reception of said second input signal to increase the second node voltage;   a voltage decreasing means connected to said second node operable in response to a control signal to control the voltage increase on said second node; and   control signal generating means coupled to said first node and to said decreasing means, operable to produce said control signal in response to excessively fast increases in the first node voltage so as to activate said decreasing means.   
     
     
       2. The circuit of claim 1 in which said control signal generating means comprises a third circuit node, a capacitive coupling means between said first and third nodes, a first resistive current path between said third node and ground, and a control signal path between said third node and said decreasing means. 
     
     
       3. The circuit of claim 2 in which said increasing means includes a second resistive current path between said second node and said high voltage supply, and a third switching means between said second node and ground and in which said decreasing means comprises fourth switching means connected between said second node and ground. 
     
     
       4. The circuit of claim 3 in which said capacitive coupling means comprises a depletion mode device with its gate connected to said first node and its source and drain connected to said third node and said first resistive path comprises a depletion mode device with its gate and source connected to ground and its drain connected to the third node and in which said second resistive path comprises a depletion mode device with its gate and source connected to the second node and its drain connected to the high voltage supply and said third switching means comprises an enhancement mode device adapted to receive said input signals on its gate and in which the fourth switching means is an enhancement mode device adapted to receive said control signal on its gate. 
     
     
       5. The circuit of claim 4 in which the first switching means comprises a depletion mode device connected to receive said input signals on its gate, and in which the second switching means comprises a depletion mode device having its control gate connected to said second node. 
     
     
       6. The circuit of claim 2 in which said capacitive coupling means comprises a depletion mode device with its gate connected to said first node and its source and drain connected to said third node and said first resistive path comprises a depletion mode device with its gate and source connected to ground and its drain connected to the third node. 
     
     
       7. The circuit of claim 1 in which said increasing means includes a second resistive current path between said second node and said high voltage supply, and a third switching means between said second node and ground. 
     
     
       8. The circuit of claim 7 in which said second resistive path comprises a depletion mode device with its gate and source connected to the second node and its drain connected to the high voltage supply and said third switching means comprises an enhancement mode device adapted to receive said input signals on its gate. 
     
     
       9. The circuit of claim 1 in which said decreasing means comprises fourth switching means connected between said second node and ground. 
     
     
       10. The circuit of claim 9 in which the fourth switching means is an enhancement mode device adapted to receive said control signal on its gate.