Page addressing mechanism

Abstract

In a computer system, paging operates and a method of use thereof are provided for extending the addressing capability of a processor by using a page register. The page register includes means for storing different codes for different operations to be performed on the memory. The memory is divided into four groups of memory within 2 n addresses such that there is paged and unpaged ROM and pages and unpaged RAM. The unpaged ROM and RAM include only a single block which is directly addressed by the n bit address bus. The paged ROM and RAM includes a plurality of blocks or pages, one of which is selected to be addressed by the page register. The page register responds to the address bus and to signals from the processor defining the memory operation to be performed by providing page signals, selecting one page of paged memory. The method of using the paging apparatus includes creating a table in the unpaged RAM of all routines in the paged memory blocks and using the table to transfer from one routine to another. Within the table is a code identifying the page in which the new routine exists and an offset into that page used to determine the address in that page of the new routine.

We claim: 
     
       1. A data addressing system for addressing data storage means comprising: processor means which provides control signals and address signals, said control signals manifesting a data movement operation to be performed and said address signals defining addresses within a confined address space,   addressable memory means for being addressed within said confined addressable space, said memory means including both read only memory addressable in a first portion of said confined addressable space and random access memory addressable in a second portion of said confined addressable space, said read only memory and random access memory being divided into an unpaged part and a plurality of paged parts, such that the address signals directly address said unpaged parts and page signals enable one of said paged parts to be addressed by said address signals;   a plurality of selectable page register means, each for storing a code, one of said page register means being selected at any time to provide said page signals as manifesting said stored code; and   page register selection means responsive to said control signals and selected address signals defining said address space portions for selecting one of said page register means wherein said page register means includes first, second and third page register means, said first page register being selected to provide said page signals whenever a read data operation occurs with respect to said read only memory, said second page register being selected to provide said page signals whenever a read data operation occurs with respect to said random access memory, and said third page register being selected to provide said page signals whenever a write data operation occurs with respect to said random access memory.   
     
     
       2. The invention according to claim 1 wherein each of said page register means stores a code related to one type of data movement operation. 
     
     
       3. The invention according to claim 2 wherein said processor means includes means for changing the code stored by said page register means. 
     
     
       4. The invention according to claim 1 wherein said processor means includes means for changing the code stored by said page register means. 
     
     
       5. The invention according to claim 1 wherein said page register means include a first page register for being selected to provide said page signals whenever a data movement operation occurs with respect to said read only memory and further includes a second page register for being selected to provide said page signals whenever a data movement operation occurs with respect to said random access memory. 
     
     
       6. The invention according to claim 5 wherein said page register selection means responds to the address signals to select one of said first and second page registers. 
     
     
       7. The invention according to claim 1 wherein said page register selection means responds to said address signals and said control signals to select one of said first, second and third page registers. 
     
     
       8. A data addressing system for addressing data storage means comprising: processor means which provides control signals and address signals, said control signals manifesting a data movement operation to be performed and said address signals defining addresses within a confined address space;   addressable memory means for being addressed within said confined addressable space, said memory means including both read only memory addressable in a first portion of said confined addressable space and random access memory addressable in a second portion of said confined addressable space, said read only memory and random access memory being divided into an unpaged part and a plurality of paged parts, such that the address signals directly address said unpaged parts and page signals enable one of said paged parts to be addressed by said address signals;   a plurality of selectable page register means, each for storing a code, one of said page register means being selected at any time to provide said page signals as manifesting said stored code; and   page register selection means responsive to said control signals and selected address signals defining said address space portions for selecting one of said page register means;   wherein said page register means includes a programmable multiword by multibit register file and logic means associated with said file for decoding signals applied thereto from said page register selection means and addressing one of said words of said file, said addressed word providing said page signals.   
     
     
       9. The invention according to claim 8 wherein said system further comprises a data bus coupled between said processor, said memory and said file, said processor means being capable of providing data signals to said data bus and for receiving data signals applied to said data bus; and wherein said file further includes logic therein for responding to the data bus signals and a write page register signal provided by said processor means for altering the code in a selected word of said file in accordance with said data bus signals.   
     
     
       10. The invention according to claim 9 wherein said system further comprises gate means coupled between said page signals and said data bus and enabled by a read page register signal provided by said processor means, to provide said page signals to said data bus. 
     
     
       11. The invention according to claim 8 wherein said selection means includes a plurality of data inputs coupled to selected address signals, a plurality of selection inputs coupled to said control signals, and at least one output at which is provided a signal related to one of said signals applied to said data input, said one signal being selected in accordance with the state of said control signals applied to said selection inputs. 
     
     
       12. The invention according to claim 11 wherein said control signals coupled to said selection inputs of said selection means manifest whether a read or a write operation is to be performed and whether the manifested operation is to be performed with respect to said memory means or said page register means, said address signals coupled to said data inputs of said selection means being chosen to select one word of said file as indicated by said control signals. 
     
     
       13. A data addressing system for addressing data storage means comprising: processor means which provides control signals and address signals, said control signals manifesting a data movement operation to be performed and said address signals defining addresses within a confined address space;   addressable memory means for being addressed within said confined addressable space, said memory means including both read only memory addressable in a first portion of said confined addressable space and random access memory addressable in a second portion of said confined addressable space, said read only memory and random access memory being divided into an unpaged part and a plurality of paged parts, such that the address signals directly address said unpaged parts and page signals enable one of said paged parts to be addressed by said address signals;   a plurality of selectable page register means, each for storing a code, one of said page register means being selected at any time to provide said page signals as manifesting said stored code; and   page register selection means responsive to said control signals and selected address signals defining said address space portions for selecting one of said page register means;   wherein said system further includes memory enabling means responsive to said address signals and said page signals for enabling one of at least a part of said unpaged read only memory, at least a part of said unpaged random access memory, at least a part of one page of said read only memory, and at least a part of at least one page of said random access memory.