Digital photodetectors

Abstract

A digital photodetector circuit having a photosensing stage connected to a depletion mode field effect transistor forming an inverter stage, increased sensitivity is achieved by then coupling the output of the photo inverter to a second photo inverter whose photosensitive element serves as the active load of an enhancement mode field effect transistor in the inverter stage. The circuit is readily fabricated in integrated structures. The circuit performance may be adjusted for responsiveness to light sensitivity and to provide selectable electrical output signal level and impedance matching including bistable performance.

Having thus described our invention, what we claim as new and desire to secure by Letters Patent is: 
     
       1. In a circuit of the type wherein a digital electrical signal is delivered in response to a change in light intensity, the improvement comprising a first and a second stage connected between a reference potential and a power source potential,   said first stage including a photosensitive member connected in series with a load between said reference potential and said power source potential providing across said photosensitive member in the presence of light a difference in potential with respect to said reference potential,     said second stage including an enhancement mode field effect transistor having the source electrode thereof connected to said reference potential and the drain thereof connected in series with a load to said power source potential,     means applying said difference of potential across said photosensitive member to the gate electrode of said enhancement mode field effect transistor in said second stage, and   output signal means delivering an output signal appearing at the drain electrode of said enhancement mode field effect transistor in said second stage.   
     
     
       2. The circuit of claim 1 wherein the load in said second stage is a second photosensitive member. 
     
     
       3. The circuit of claim 1 wherein the load in said first stage is a depletion mode field effect transistor. 
     
     
       4. The circuit of claim 1 wherein the load in said second stage is a depletion mode field effect transistor. 
     
     
       5. The circuit of claim 1 wherein the load in each said first and said second stage is a depletion mode field effect transistor. 
     
     
       6. The circuit of claim 2 wherein the load in each said first and said second stage is a depletion mode field effect transistor. 
     
     
       7. The circuit of claim 1 wherein said photosensitive member is a photoconductor. 
     
     
       8. The circuit of claim 1 wherein said photosensitive member is a phototransistor. 
     
     
       9. The circuit of claim 1 wherein said photosensitive member is a PIN diode. 
     
     
       10. The circuit of claim 2 wherein said photosensitive member is a photoconductor. 
     
     
       11. The circuit of claim 2 wherein said photosensitive member is a phototransistor. 
     
     
       12. The circuit of claim 2 wherein said photosensitive member is a PIN diode.