ECL MOS Buffer circuits

Abstract

An input buffer to which an ECL logic swing is applied through a voltage level shifter to one input of a differential pair of switching devices, the other input of the differential pair being a voltage level shifted by the same amount from an ECL logic reference voltage. The output across a load device coupling one of the switching devices to a collector voltage source drives the input of a conventional inverter coupling a reduced MOS logic voltage supply to the collector voltage source. An output buffer to which a reduced MOS voltage swing logic input is applied to the input of a conventional inverter coupling a reduced MOS logic voltage supply to a collector voltage source. The output of the inverter is applied to one input of a differential pair of switching devices having the other input thereto held at a reference level defined by a voltage divider. The output of the differential pair across a load device coupling one of the switching devices to the collector voltage source is level shifted through another switching device to the circuit output.

I claim: 
     
       1. An input buffer for converting a first logic voltage signal having a respective logic high level and a logic low level present on an input line to a second logic voltage signal having a respective logic high level and a logic low level present on an output line, wherein the voltage difference between said first signal high level and low level is different from the voltage difference between said second signal high level and low level, said respective logic high levels being substantially the same, comprising: first and second switching devices having common emitter contacts and respective first and second collector and base contacts thereof, said first and second collector contacts being respectively connected to a collector voltage source line and an output node,   a current source coupling said common emitter contacts to an emitter voltage source line,   first and second level shifting means for coupling said input line and a logic reference voltage respectively to said emitter voltage source line for biasing said first and second base contacts,   a load device coupling said output node to said collector voltage source line, and   a logic inverter coupling a supply voltage line to said collector voltage source line and having input and output terminals thereof, said input terminal being connected to said output node and said output terminal being said output line.   
     
     
       2. The input buffer of claim 1, wherein said first and second switching devices are NPN bipolar transistors. 
     
     
       3. The input buffer of claim 1 wherein said current source comprises a resistor and a series connected transistor having a reference voltage input thereto. 
     
     
       4. The input buffer of claim 3 wherein said series connected transistor is a bipolar transistor. 
     
     
       5. The input buffer of claim 1 wherein said first and second level shifting means comprise series connected diodes. 
     
     
       6. The input buffer of claim 1 wherein said load device is a resistor. 
     
     
       7. The input buffer of claim 1 wherein said logic inverter comprises a CMOS inverter. 
     
     
       8. The logic inverter of claim 1 wherein said supply voltage on said supply voltage line is substantially minus two volts with respect to said collector voltage source line. 
     
     
       9. An output buffer for converting a first logic voltage signal having a respective logic high level and a logic low level present on an input line to a second logic voltage signal having a respective logic high level and a logic low level present on an output line, wherein the voltage difference between said first signal high level and low level is different from the voltage difference between said second signal high level and low level, said respective logic high levels being substantially the same, comprising: first and second switching devices having common emitter contacts and first and second collector and base contacts respectively, said first and second collector contacts being respectively connected to a collector voltage source node and an output node,   a current source coupling said common emitter contacts to an emitter voltage source node,   a load device coupling said output node to said collector voltage source node,   a logic inverter coupling a supply voltage node to said collector voltage source node and having input and output terminals thereof, said input terminal being said input line and said output terminal connected to said first base contact,   a voltage divider coupling said supply voltage node to said collector voltage source node for biasing said second base contact,   a third switching device having third collector, base and emitter contacts respectively connected to said collector voltage source node, said output node and said output line.   
     
     
       10. The output buffer of claim 9 wherein said first, second and third switching devices are NPN bipolar transistors. 
     
     
       11. The output buffer of claim 9 wherein said current source comprises a resistor and a series connected transistor having a reference voltage input thereto. 
     
     
       12. The output buffer of claim 11 wherein said series connected transistor is a bipolar transistor. 
     
     
       13. The output buffer of claim 9 wherein said logic inverter comprises a CMOS inverter. 
     
     
       14. The output buffer of claim 9 wherein said supply voltage at said supply voltage node is substantially -2 volts with respect to said collector voltage source line. 
     
     
       15. The output buffer of claim 9 wherein said load device is a resistor. 
     
     
       16. The output buffer of claim 9 wherein said voltage divider comprises series connected resistors.