Channel charge compensation switch with first order process independence

Abstract

In the present invention, channel charge compensation is achieved in a MOS switch comprising two MOSFETs connected in parallel and a compensating MOSFET placed on the semiconductive substrate in precise symmetry with the two switching FETs, each of the FETs being designed to have the same channel charge storing capacity. Accordingly, first order variations in oxide thickness or in gate width across the surface of the semiconductive substrate do not affect the accuracy with which channel charge is compensated in the invention. The compensating FET is switched in complementary fashion with the two switching FETs so that it absorbs one-half of the channel charge expelled from the switching FETs when they are turned off, thus preventing this charge from upsetting other components in the circuit such as precision storage capacitors connected to the switch.

What is claimed is: 
     
       1. A precision semiconductor switch comprising: an input node and an output node;   a pair of switching transistors, each comprising a source and a drain, the source/drain current paths of the switching transistors being connected between the input and output nodes so that said switching transistors are connected in parallel with one another;   a compensating transistor comprising a compensating source and drain, said compensating transistor having its source and drain both connected together and to said output node; and   means for applying a control signal to the gates of said switching transistor pair and means for applying the logical complement of said control signal to the gate of said compensating transistor.   
     
     
       2. The switch of claim 1 further comprising a second compensating transistor comprising a second compensating source and drain, its source and drain both being connected together and to said input node. 
     
     
       3. The switch of claim 1 wherein said compensating transistor has a channel charge storage capacity equal to approximately one-half the channel charge storage capacity of the combination of said pair of switching transistors. 
     
     
       4. The switch of claim 2 wherein said compensating transistor pair have a combined channel charge capacity equal to approximately the combined channel charge storage capacity of said switching transistor pair. 
     
     
       5. The switch of claim 1 wherein each of said transistors comprises a gate, each gate of said switching transistor pair being connected together, said switch further comprising a switching node and an inverter, said switching node being connected to each switching transistor gate and being connected through said inverter to the gate of said compensating transistor. 
     
     
       6. The switch of claim 1 wherein each of said transistors comprises an n-channel field effect transistor, said switch further comprising a plurality of p-channel transistors having their sources and drains connected to the sources and drains, respectively, of the corresponding n-channel transistors. 
     
     
       7. The switch of claim 1 wherein said transistors are formed on a common semiconductive substrate and are arranged thereon in a symmetrical fashion. 
     
     
       8. The switch of claim 1 wherein said transistors are formed on a common semiconductive substrate, said switching transistors being formed with space therebetween, and said compensating transistor being located in said space whereby the distance from said compensating transistor to each of said switching transistors is approximately equal. 
     
     
       9. The switch of claim 2 wherein said transistors are formed on a semiconductive substrate, said switching transistors being a first transistor pair and said compensating transistors being a second transistor pair, one of said pair being adjacent one another and separating the transistors of the other pair. 
     
     
       10. The switch of claim 6 including a plurality of gates individually associated with each of said transistors wherein the gates of the n-channel switching transistors and of the p-channel compensating transistor are connected together and to receive a switching signal, and wherein the gates of the p-channel switching transistors and of the n-channel compensating transistor are connected together and to receive an inverted switching signal. 
     
     
       11. The switch of claim 2 wherein each of said transistors comprises an n-channel transistor, said switch further comprising a plurality of p-channel transistors having their sources and drains connected to the sources and drains, respectively, of corresponding ones of said n-channel transistors, said switch further including a plurality of gates associated with each of said transistors, and wherein the gates of the n-channel switching transistors and with the p-channel compensating transistors are connected together to receive a switching signal, and wherein the gates of the p-channel switching transistors and of the n-channel compensating transistors are connected together and to receive an inverted switching signal. 
     
     
       12. A precision semiconductor switch comprising: an input node and an output node;   a pair of field effect transistors connected in parallel, the source/drain current paths of the switching transistors being connected between said input and output nodes as a switch across said nodes;   a compensating field effect transistor having its source and drain both connected together and to either said input or output node; and   means for applying a control signal to the gates of said transistor pair and means for applying the logical compliment of said control signal to the gate of said compensating transistor.