Communication adapter circuit

Abstract

A communication adapter circuit (10) is connected to a processor through a data bus (12)and a control bus (14). Data and control signals are provided through the buses (12,14) to a timer circuit (18), a programmable peripheral interface circuit (20), an asynchronous and bisynchronous control circuit (22) and an SDLC/HDLC control circuit (24). Each of the control circuits (22, 24) includes parallel-to-serial and serial-to-parallel conversion circuitry. A clock select circuit (32) operates in conjunction with the timer circuit (18) and the programmable peripheral interface circuit (20) to establish a data transmission rate for the data flow through the adapter circuit (10). From the control circuits (22, 24) the data is transmitted through a bi-directional serial line (44) to a dual modem switch (56). From the switch (56) the data is transmitted to either an EIA interface circuit (60) to a conventional modem or through a line (64) to an internal modem.

We claim: 
     
       1. A multi-protocol communication adapter circuit for interfacing a processor with a modem for providing communication between the processor and a remote terminal, comprising: a data transfer bus connected to said processor;   a plurality of control lines connected to said processor;   an asynchronous and bisynchronous control circuit connected to said data transfer bus and to said modem for controlling data transfer between said processor and said remote terminal under asynchronous and bisynchronous protocols, respectively, said asynchronous and bisynchronous control circuit connected to at least one of said control lines for receiving command signals from said processor;   an SDLC (Synchronous Data Line Control) control circuit connected to said data transfer bus and to said modem for controlling data transfer between said processor and said remote terminal under SDLC protocol, said SDLC control circuit connected to at least one of said control lines for receiving command signals from said processor, and having a clock recovery mechanism for generating a data clock signal;   means responsive to command signals from said processor for generating a clock select command signal representing the rate of data transfer between said processor and said remote terminal; and   a clock selection circuit connected to said SDLC control circuit to receive said data clock signal, and to said means for generating to receive a clock select command signal, said clock selection circuit also connected to said asynchronous and bisynchronous control circuit for providing said data clock signal thereto during operation under said bisynchronous protocol, and for providing said data clock signal to said SDLC control circuit during operation under SDLC protocol.   
     
     
       2. The circuit recited in claim 1 for interfacing the processor to one of two modems further comprising a dual modem switch connected to said asychronous and bisynchronous control circuit and said SDLC control circuit for selectively connecting said control circuits to either one of the two modems. 
     
     
       3. The circuit recited in claim 1 including a wrap logic circuit connected to the modem, said asynchronous and bisynchronous control circuit and said SDLC control circuit for selectively routing test data between said control circuits for testing the operation of said communication adapter circuit. 
     
     
       4. The circuit recited in claim 1 wherein said clock recovery mechanism of said SDLC control circuit is a digital phase locked loop. 
     
     
       5. The circuit recited in claim 1 wherein said means for generating includes a timer circuit and a programmable peripheral interface circuit. 
     
     
       6. A method for providing communication between a processor and a remote terminal through modems by use of one of a plurality of communication protocols, comprising the steps of: transmitting command signals through control lines from said processor to an asynchronous and bisynchronous control circuit for initialization thereof for operation in either an asynchronous or bisynchronous communication protocol;   transmitting command signals through control lines from said processor to an SDLC (Synchronous Data Line Control) control circuit for initialization thereof for operation in an SDLC communication protocol, said SDLC control circuit having a clock recovery mechanism for generating a data clock signal;   transmitting command signals through control lines from said processor to a clock selection circuit for setting a rate for data transfer through said asynchronous and bisynchronous control circuit or said SDLC control circuit;   applying said data clock signal from said SDLC control circuit to said clock selection circuit;   applying said data clock signal from said clock selection circuit to said asynchronous and bisynchronous control circuit during operation thereof under said bisynchronous protocol; and   transferring data between said processor and said remote terminal through said modems and said asynchronous and bisynchronous control circuit at the data transfer rate selected by said processor.   
     
     
       7. The method recited in claim 6 including the steps of transferring data in a parallel format between said processor and said control circuits and transferring data in a serial format between said control circuits and said modems. 
     
     
       8. The method recited in claim 6 including the step of testing said control circuits by transferring the data on the transmit line from the control circuit selected by said processor to the receiver line for the selected control circuit.