Digital data sense amplifier and signal differentiator

Abstract

A digital data sense amplifier is disclosed for detecting small signal outputs from a storage media or from input sensors and comprises a differential amplifier whose outputs are coupled via two capacitors to an offset circuit which generates two offsets which in turn are fed to two comparators, one for a positive signal threshold and one for a negative signal threshold. This results in peak to peak data sensing in a noisy signal environment. An alternative embodiment differentiates an inputted analog signal and outputs a digital representation of the first derivative, or rate of change of said analog signal.

What is claimed is: 
     
       1. An asynchronous system for sensing digital data from an input signal comprising: first comparator means for determining the minimum level of said input signal, said first comparator means having a resettable offset, and producing a digital output signal when said input signal reaches a first predetermined level;   second comparator means for producing a digital output signal when said input signal exceeds said minimum level by a second predetermined level, said second comparator means having a resettable offset; and   feedback means coupled to said first comparator means output for resetting said first and said second comparator means offsets to the value of said input signal whenever said first comparator means output signal is present.   
     
     
       2. The system of claim 1 wherein said second comparator output is coupled to said feedback means, and said first and said second comparator means offsets are reset to zero when said input signal exceeds either said first or said second predetermined levels. 
     
     
       3. The system of claim 1 wherein said feedback means includes a NAND gate having an input coupled to said first comparator means output and an input coupled to means for selectively enabling said feedback means. 
     
     
       4. The system of claim 2 wherein said feedback means includes a NAND gate having an input coupled to said first comparator means output, an input coupled to said second comparator means output, and an input coupled to means for selectively enabling said feedback means. 
     
     
       5. The system of claim 1 wherein said input signal is produced by means for retrieving data from a storage medium.