Semiconductor regeneration/precharge device

Abstract

A semiconductor device includes: a pair of first and second data lines charged to a predetermined potential during a precharge period; a sense amplifier for sensing the potential of the pair of data lines during an active period; and a regeneration circuit which charges the first and second data lines to the predetermined potential and maintain the potential of the higher potential data line after the sense amplifier senses during the active period.

What is claimed is: 
     
       1. A semiconductor device comprising: a first source of power; a pair of first and second data lines charged to a predetermined potential during a precharge period;   sense amplifier means coupled to said first power source for sensing, during an active period, a potential between the pair of said first and second data lines; and   regeneration means coupled to said first power source and connected to said first and second data lines for charging said first and second data lines to said predetermined potential during said precharge period and for maintaining the potential of the one of the data lines having a higher potential after said sense amplifier senses during said active period.   
     
     
       2. A semiconductor memory device according to claim 1 wherein said regeneration means comprises: (a) a first transistor which is coupled at its drain to said first power source and which receives at its gate a pulse signal having a low level during said precharge period;   (b) second and third transistors which are connected at their drains to the source of said first transistor and at their sources to said first and second data lines;   (c) a fourth transistor which is connected at one of the drain and source electrodes to the gate of said second transistor and at the other electrode to said first data line;   (d) a fifth transistor which is connected at one of the drain and source electrodes to the gate of said third transistor and at the other electrode to said second data line;   (e) a first capacitor element which is connected at one end to the gate of said second transistor and receives at the other end of first pulse signal having a high level during said precharge period; and   (f) a second capacitor element which is connected at one end to the gate of said third transistor and receives at the other end said first pulse signal.   
     
     
       3. A semiconductor memory device according to claim 1 wherein said regeneration means comprises: (a) first and second transistors coupled at their drains to said first power source and at their sources to said first and second data lines;   (b) a third transistor which is connected at one of the drain and source electrodes to the gate of said first transistor and at the other electrode to said first data line;   (c) a fourth transistor which is connected at one of the drain and source electrodes to the gate of said second transistor and at the other electrode to said second data line;   (d) a first capacitor element which is connected at one end to the gate of said first transistor and receives at the other end a first pulse signal having a high level during said precharge period; and   (e) a second capacitor element which is connected at one end to the gate of said second transistor and receives at the other end said first pulse signal.   
     
     
       4. A semiconductor memory device according to claim 3, wherein said transistors are all of the enhancement type and said third and said fourth transistors are coupled at their gates to said first power source. 
     
     
       5. A semiconductor memory device according to claim 3, wherein said transistors are all of the enhancement type and said third and said fourth transistors are coupled at their gates to a second pulse signal which is in synchronism with said first pulse signal applied to said first and second capacitor elements. 
     
     
       6. A semiconductor memory device according to claim 3, wherein said first and second transistors are of the enhancement type, and said third and fourth transistors are of the depletion type and coupled at their gates to a second power source. 
     
     
       7. A semiconductor memory device according to claim 1 wherein said regeneration means comprises: (a) a first transistor which is coupled at its drain to said first power source, and which receives at its gate a pulse signal having a high level during said precharge period;   (b) second and third transistors which are connected at their drains to the source of said first transistor and at their sources to said first and second data lines;   (c) a fourth transistor which is connected at one of the drain and source electrodes to the gate of said second transistor and at the other electrode to said first data line;   (d) a fifth transistor which is connected at one of the drain and source electrodes to the gate of said third transistor and at the other electrode to said second data line;   (e) a first capacitor element which is connected to the gate of said second transistor and receives at the other end a first pulse signal having a high level during said precharge period; and   (f) a second capacitor element which is connected at one end to the gate of said third transistor and receives at the other end said first pulse signal.   
     
     
       8. A semiconductor memory device according to claim 1 wherein said regeneration means includes means for short circuiting said first and second data lines. 
     
     
       9. A semiconductor memory device according to claim 1 wherein said regeneration means includes means for forming a charge path to said first and second data lines during said precharge period. 
     
     
       10. A semiconductor memory device according to any one of claims 1, 2, 3 or 7 wherein said sense amplifier means comprises: (a) a first sense amplifier transistor which is connected at its drain to said first power source and receives at its gate a precharge pulse;   (b) second and third sense amplifier transistors which are connected at their drains to the source of said first sense amplifier transistor, at their sources to said first and second data lines, and receive at their gates said precharge pulse;   (c) a fourth sense amplifier transistor which is connected at its drain to said first data line and at its gate to said second data line;   (d) a fifth sense amplifier transistor which is connected at its drain to said second data line and at its gate to said first data line;   (e) a second source of power; and   (f) a sixth sense amplifier transistor which is connected at its drain to the sources of said fourth and fifth sense amplifier transistors, is coupled at its source to said second power source, and receives at its gate a drive pulse.   
     
     
       11. A semiconductor memory device according to any one of claims 1, 2, 3 or 7 wherein said sense amplifier means comprises: (a) first and second sense amplifier transistors which are coupled at their gates to said first power source, are connected at their sources to said first and second data lines, and receive at their gates a precharge pulse;   (b) a third sense amplifier transistor which is connected at its drain to said first data line and at its gate to said second data line;   (c) a fourth sense amplifier transistor which is connected at its drain to said second data line and at the gate to said first data line;   (d) a second source of power; and   (e) a fifth sense amplifier transistor which is connected at its drain to the sources of said third and fourth sense amplifier transistors, is coupled at its source to said second power source and receives at its gate a drive pulse.   
     
     
       12. A semiconductor memory device according to any one of claims 1, 2, 3 or 7 wherein said sense amplifier means comprises: (a) first and second sense amplifier transistors which are coupled at their drains to said first power source, are connected at their sources to said first and second data lines, and receive at their gates a precharge pulse;   (b) a third sense amplifier transistor which is connected at its drain to said first data line and at its gate to said second data line;   (c) a fourth sense amplifier transistor which is connected at its drain to said second data line and at its gate to said first data line;   (d) a fifth sense amplifier transistor which is connected at one of the drain and source electrodes to said first data line and at the other electrode to said second data line;   (e) a second source of power; and   (f) a sixth sense amplifier transistor which is connected at its drain to the sources of said third and fourth sense amplifier transistors, coupled at its source to said second power source, and receives at its gate a drive pulse.   
     
     
       13. A semiconductor memory device according to claim 2 or 7, wherein said transistors are all of the enhancement type and said fourth and fifth transistors are coupled at their gates to said first power source. 
     
     
       14. A semiconductor memory device according to claim 2 or 7, wherein said transistors are all of the enhancement type and said fourth and fifth transistors are coupled at their gates to a second pulse signal which is in synchronism with said first pulse signal applied to said first and second capacitance elements. 
     
     
       15. A semiconductor memory device according to claim 2 or 7, wherein said first to third transistors are of the enhancement type, and said fourth and fifth transistors are of the depletion type and coupled at their gates with a second power source. 
     
     
       16. A semiconductor device comprising: first and second sources of power:   a pair of first and second data lines charged to a predetermined potential during a precharge period;   regeneration means including first transistor which is coupled at its drain to said first power source, receives at its gate a first pulse signal having a high level period during said precharge period, second and third transistors which are connected at their drains to the source of said first transistor, and at their sources to said first and second data lines, a fourth transistor which is connected at one of the drain and source electrodes to the gate of said second transistor, at the other electrode to said first data line, and has at its gate said first power source, a fifth transistor which is connected at one of the drain and source electrodes to the gate of said third transistors, at the other electrode to said second data line, and has at its gate the first power source, a first capacitor element which is connected at one end to the gate of said second transistor and receives at the other end a second pulse signal having a high level during said precharge period, and a second capacitor element which is connected at one end to the gate of said third transistor and receives at the other end said second pulse signal; and   sense amplifier means including a sixth transistor which is connected at its drain to the first power source, and at its gate to a precharge pulse, seventh and eighth transistors which are connected at their drains to the source of said sixth transistor, at their sources to said first and second data lines, and receive at their gates said precharge pulse, a ninth transistor which is connected at its drain to said first data line and at its gate to said second data line, a tenth transistor which is connected at its drain to said second data line and at its gate to said first data line, and an eleventh transistor which is connected at its drain to the sources of said ninth and tenth transistors, coupled at its source to said second power source and receives at its gate a drive pulse.