High voltage bubble memory pulse generator output stage

Abstract

A circuit for providing the gate of a bubble memory with a precision current pulse at a high voltage is manufactured using a low voltage process; i.e. BV ceo is approximately 18 volts. In order to accomplish this, first and second voltage level shifting stages are cascoded and the output transistors thereof are used as Zener level shifters each level shifting downward by a BV ceo when only a small voltage is dropped across the load. If the voltage drop across the load increases, the cascoded output transistors may enter their active region and are prevented from going into saturation by saturation clamps so as to not introduce unwanted delays in the rise or fall times of the current pulse.

We claim: 
     
       1. A monolithic integrated circuit for receiving a high voltage and generating therefrom a substantially lower voltage at a node, comprising: first means for generating a reference voltage; and   at least one voltage level shifting stage including an output transistor having a collector coupled to said high voltage, an emitter coupled to said node, and having a base, said output transistor for acting as a BV ceo  level shifter when the collector-emitter voltage reaches BV ceo  where BV ceo  is the transistor's collector-emitter breakdown voltage with an open base, and for providing a predetermined level shift substantially less than BV ceo  when the collector-emitter voltage falls to said predetermined level, and for operating in its active region when its collector-emitter voltage is between BV ceo  and said predetermined level.   
     
     
       2. A circuit according to claim 1 wherein said voltage level shifting stage further includes diode means coupled between said first means and the base of said output transistor which is reverse biased when the voltage at the emitter of said output transistor is above said reference voltage less a predetermined amount and becomes forward biased when the voltage at the emitter of said output transistor is less than said reference voltage by a predetermined amount so as to supply base current to said output transistor. 
     
     
       3. A circuit according to claim 2 wherein said voltage level shifting stage further includes a drive transistor coupled between said diode means and said output transistor in Darlington pair forming relationship with said output transistor, said drive transistor having a base coupled to said diode means, a collector coupled to the collector of said output transistor and an emitter coupled to the base of said output transistor. 
     
     
       4. A circuit according to claim 3 wherein said voltage level shifting stage further comprises a saturation clamp coupled to said first means, to said drive transistor, and to said output transistor, to limit the voltage between the collector-emitter of said output transistor to said predetermined amount when the output transistor is operating in its active mode so as to prevent said drive transistor and said output transistor from going into saturation. 
     
     
       5. A circuit according to claim 4 wherein said saturation clamp is a first transistor having an emitter coupled to said reference voltage, and a collector and base coupled to the collectors of said output and drive transistors. 
     
     
       6. A circuit according to claim 5 wherein said diode means comprises a second transistor having an emitter coupled to said reference voltage and having a base and collector coupled to the base of said drive transistor. 
     
     
       7. A circuit for presenting a voltage below a predetermined value to a current pulse generator, which generator supplies a current pulse to a load coupled between said circuit and a source of supply voltage substantially greater than said predetermined value, comprising: first means for generating a reference voltage; and   at least one voltage level shifting stage coupled between said load and said current pulse generator, said at least one voltage level shifting stage including an output transistor having a collector coupled to said load, an emitter coupled to said load, and having a base for receiving base drive, said output transistor for acting as a BV ceo  level shifter when its collector-emitter's voltage reaches BV ceo  where BV ceo  is a transistor's collector-emitter breakdown voltage with an open base, and for providing a predetermined level shift substantially less than BV ceo  when its collector-emitter voltage falls to said predetermined level, and for operating in its active region when its collector-emitter voltage is between BV ceo  and said predetermined level.   
     
     
       8. A circuit according to claim 7 wherein said voltage level shifting stage further includes diode means coupled between said first means and the base of said output transistor which is reversed biased when the voltage at the emitter of said output transistor is above said reference voltage less a predetermined amount and becomes forward biased when the voltage at the emitter of said output transistor is less than said reference voltage by a predetermined amount so as to supply base drive to said output transistor. 
     
     
       9. The circuit according to claim 8 wherein said at least one voltage level shifting stage further includes a drive transistor coupled between said diode means and said output transistor in Darlington pair forming relationship with said output transistor, said drive transistor having a base coupled to said diode means, a collector coupled to the collector of said output transistor and an emitter coupled to the base of said output transistor. 
     
     
       10. A circuit according to claim 9 wherein said at least one voltage level shifting stage further includes a saturation clamp coupled to said first means, said drive transistor and said output transistor to limit the voltage between the collector-emitter of said output transistor to said predetermined amount when said output transistor operating in its active mode so as to prevent said output transistor and said drive transistor from going into saturation. 
     
     
       11. A circuit according to claim 10 wherein said saturation clamp is a first transistor having an emitter coupled to said reference voltage, a collector coupled to the collector of said output transistor and a base coupled to the collector of said drive transistor.