Multiple synchronous counters with ripple read

Abstract

A system for reading out the contents of multiple counters onto a common bus comprising a plurality of synchronous binary counters arranged in a ring with each counter having N corresponding stages each having an output terminal on which appears the contents of the stage, an input terminal, and a clock pulse input terminal, with each stage responsive to a clock pulse supplied to its clock input terminal to transfer the signal logic level on its input terminal to its output terminal and with the output terminals of the stages of a given counter comprising the common bus. Also provided is a clock pulse source for supplying clock pulses to all of the clock input terminals and a switching signal source for generating a switching pulse. A switch associated with each stage is responsive to the switching pulse to connect the output terminal of each stage to the input terminal of the corresponding stage of the next adjacent counter in the ring of counters.

What is claimed is: 
     
       1. A system for reading out the contents of multiple counters onto the leads of a common bus comprising: a plurality of first to Mth synchronous binary counters with each counter having N corresponding stages, each having an output terminal on which appears the contents of said stage, an input terminal, and a clock pulse input terminal, with each stage responsive to a clock pulse supplied to its clock pulse input terminal to transfer the signal logic level on its input terminal to its output terminal and with the output terminals of the corresponding stages of Mth counter comprising said common bus;   clock pulse generating means for supplying clock pulses simultaneously to all of said clock input terminals;   means for generating a switching pulse;   switching means responsive to said switching pulse for connecting said output terminal of each stage simultaneously and in parallel to the input terminal of the corresponding stage of the next adjacent counter in said ring of counters and including the connections of the output terminals of the corresponding stages of the Mth binary counter to the input terminals of the corresponding stages of said first synchronous binary counter.   
     
     
       2. A system for successively reading out in parallel manner the contents of multiple counters onto a common multiplexed bus comprising: a plurality of M synchronous binary counters arranged generally in a row and each having N corresponding stages with each stage having an output terminal on which appears the contents of said stage, an input terminal, and a clock pulse input terminal, with each stage responsive to a clock pulse of repetition rate R supplied to its clock input terminal to transfer the signal logic level on its input terminal to its output terminal, and with the output terminals of the stages of the Mth counter in the row of counters each comprising said one of the leads of the common multiple lead bus;   signal generating means for generating and supplying N clock pulses to all of said clock pulse input terminals and for generating a switching signal having a duration which can equal N clock pulses; and   switching means responsive to said switching signal for the duration of said switching signal to connect said output terminal of each stage to the input terminal of the corresponding stage of the next adjacent counter in said row of counters.   
     
     
       3. A system for reading out the contents of corresponding stages of multiple counters each onto a separate lead of a common data bus and comprising: a plurality of storage elements arranged in a matrix of rows and columns of storage elements with each storage element having an input terminal, an output terminal, and a clock input terminal and responsive to a clock pulse supplied to its clock input terminal to transfer the signal on its input terminal to its output terminal;   a plurality of first logic means each interconnecting a column of storage elements to form a counter with each storage element having a second input terminal responsive to an input pulse supplied thereto followed by a clock pulse supplied to the clock input terminals of said column of storage elements to advance the count in said counter;   a common data bus having a separate lead connected to each output terminal of the storage elements of a given counter;   means for generating a switching signal; and   switching means responsive to said switching signal to connect the output terminals of all of the storage elements in each counter to the input terminals of the corresponding adjacent storage elements in the same row of storage elements to form a plurality of rows of shift registers.   
     
     
       4. A system for successively shifting the contents of each stage of a counter in a ring of counters into the corresponding stage of the adjacent counter and comprising: a plurality of M synchronous binary counters arranged in a ring with each counter having N corresponding stages each having an output terminal on which appears the contents of said stage, an input terminal, and a clock pulse input terminal, with each stage responsive to a clock pulse supplied to its clock input terminal to transfer the signal logic level on its input terminal to its output terminal, and with switching means for connecting the output terminal of each stage of each counter to the corresponding input of the adjacent counter;   signal generating means for generating and supplying clock pulses to all of said clock input terminals and for generating a switching signal having a duration equal to M clock pulses or less; and   switching means responsive to said switching signal to connect said output terminal of each stage of each counter to the input terminal of the corresponding stage of the next adjacent counter in said ring of counters.