Differential amplifier having a compensation current injection selector network

Abstract

A differential amplifier is provided having a pair of input transistors with first electrodes connected to a first voltage potential through a first current source, a second pair of electrodes providing a pair of input terminals for the differential amplifier, and a third pair of electrodes connected to a pair of terminals, the current produced by the first current source passing through the first and third electrodes of the pair of input transistors into the pair of terminals in a ratio related to the difference in voltage of input signals fed to the pair of input terminals and the degree of mismatch in the pair of input transistors. A selector network injects a compensation current substantially equal to the difference in the currents passing through the pair of input transistors when the voltages at the pair of inputs are equal, and which results from a mismatch in such pair of input transistors, into a selected one of the pair of terminals. A balanced current mirror has an input coupled to a first one of the pair of terminals and an output coupled to a second one of the pair of terminals for forcing current passing into the second one of the pair of terminals through the output of the current mirror to be substantially equal to current passing into the first one of the pair of terminals to the input of the current mirror with an output current passing from the second one of the pair of terminals to an output stage, such output current being substantially zero when the voltages at the pair of input terminals are equal to thereby compensate for the difference in the currents passing through the pair of input transistors as a result of the mismatch in the pair of input transistors.

What is claimed is: 
     
       1. A differential amplifier comprising: (a) means, including a pair of transistors having first electrodes adapted for coupling to a first current source, a pair of input electrodes, and a pair of output electrodes coupled to a pair of output terminals, for feeding a pair of currents to the pair of output terminals from the first current source in a ratio related to the difference in voltages of input signals fed to the pair of input electrodes, such pair of currents having a difference D therebetween when the voltages at the pair of inputs are equal;   (b) a selector network means for adding a compensating current substantially equal to the difference D to the current fed to one of the pair of output terminals; and   (c) means coupled to the pair of output terminals for equalizing the currents passing from the pair of output terminals producing an output current substantially zero when the voltages fed to the pair of input electrodes are equal to compensate for the difference D in the pair of currents passing through the pair of input transistors when such voltages are equal.   
     
     
       2. The amplifier recited in claim 1 wherein the selector network means includes: a plurality of additional current sources, each one thereof being matched over a predetermined range of operating temperatures, to the first current source; and means fed by the plurality of additional current sources, for passing a selected portion of the current produced by the additional current sources to the selected one of the pair of outputs as the compensating current and for diverting the remaining unselected portion of the total current produced by the plurality of additional current sources from the pair of outputs to a second voltage potential. 
     
     
       3. The amplifier recited in claim 2 wherein the equalizing means includes a pair of bipolar transistors with collector electrodes coupled to the pair of outputs, base electrodes coupled together and emitter electrodes coupled to the second voltage potential. 
     
     
       4. The amplifier recited in claim 3 wherein the selector means includes a transistor having: a plurality of input electrodes coupled to the plurality of additional current sources, and a selected one, or ones thereof coupled to a selected one of the pair of outputs; a second electrode coupled to the second voltage potential; and a third electrode coupled to the second one of the pair of outputs through a bias circuit. 
     
     
       5. The amplifier recited in claim 4 wherein the bias circuit includes means for providing a bias voltage between the second and third electrodes of the transistor of the selector network, means to inhibit current from the selected portion of the total current produced by the plurality of current sources from passing through such transistor and for allowing the remaining unselected portion of such total current to pass through the first and third electrodes of such transistor to the second voltage potential. 
     
     
       6. The amplifier recited in claim 5 wherein the transistor of the selector means is a bipolar transistor and wherein the second and third electrodes are base and collector electrodes, respectively. 
     
     
       7. The amplifier recited in claim 6 wherein the bias circuit includes a pair of transistors having first and second electrodes serially connected between the first and second voltage potentials. 
     
     
       8. The amplifier recited in claim 7 wherein a first one of the pair of transistors of the bias circuit has a third electrode coupled to the first voltage potential and a second one of the pair of transistors of the bias circuit has a third electrode coupled to the second one of the pair of outputs and the first electrode coupled to the base electrode of the bipolar transistor of the selector network means. 
     
     
       9. The amplifier recited in claim 8 wherein the input electrodes of the transistor of the selector means are emitter electrodes. 
     
     
       10. A differential amplifier comprising: (a) means, including a pair of transistors having first electrodes adapted for coupling to a first current source, a pair of input electrodes, and a pair of output electrodes coupled to a pair of output terminals, for feeding a pair of currents to the pair of output terminals from the first current source in a ratio related to the difference in voltages of input signals fed to the pair of input electrodes, such pair of currents having a difference D therebetween when the voltages at the pair of inputs are equal;   (b) a selector network means for adding a compensating current substantially equal to the difference D to the current fed to one of the pair of output terminals; and   (c) means having an input coupled to a first one of a pair of the output terminals and an output coupled to a second one of the pair of output terminals at a junction, for equalizing the current passing from the first one of the pair of output terminals to the input of the equalizing means and a current passing from the junction to the output of the equalizing means producing a current out of the junction equal to the difference between the current passing out of the pair of output terminals to the junction and the current passing from the junction to the output of the equalizing means, such current being substantially zero when the voltages fed to the pair of input electrodes are equal to compensate for the difference D in the pair of current passing through the pair of input transistors when such voltages are equal.