Shared virtual address translation unit for a multiprocessor system

Abstract

A virtual storage data processing system having an address translation unit shared by a plurality of processors, located in a memory control unit connected to a main memory is disclosed. One of the plurality of processors is a job processor which accesses the main memory with a virtual address to execute an instruction and includes a cache memory which is accessed with a virtual address. One of the plurality of processors is a file processor which accesses the main memory with a virtual address to transfer data between the main memory and an external memory. The cache memory receives the virtual address when the file processor writes to the main memory and if it contains a data block corresponding to the virtual address, it invalidates the corresponding data block. The address translation unit translates the address differently for the access from the file processor and the accesses from other processors.

What is claimed is: 
     
       1. A virtual storage data processing system comprising: (a) a main memory for storing data and instructions;   (b) an external memory for storing data and instructions to be stored in said main memory;   (c) a job processor for accessing said main memory with virtual addresses to access data and instructions stored therein;   (d) a file processor connected to external memory for accessing said main memory with virtual addresses to transfer data and instructions between said main memory and said external memory;   (e) a memory controller connected to said main memory and including an address translation unit which translates virtual addresses from said job processor and said file processor into physical addresses and means for controlling accesses to said main memory with the translated physical addresses;   (f) a common bus for connecting said job processor and file processor with said memory controller; and   (g) the address translation unit of said memory controller having means providing status flags indicating that said file processor is transferring a partial data block between said main memory and said external memory, and means responsive to said status flags being set for causing said address translation unit to allow an access from said file processor to said data block, while inhibiting an access from said job processor to said data block and for outputting a page fault signal indicating that said data block does not exist in said main memory.   
     
     
       2. A virtual storage data processing system according to claim 1 wherein said memory controller includes: (a) means having a first register for latching a virtual address transferred through the common bus from said file processor and said job processor,   (b) said address translation unit having means for translating the virtual address latched in said first register to a physical address; and   (c) means having a second register for storing the physical address from said address translation unit, for effecting sequential latching of the virtual address in said first register, including means for effecting address translation of the content of said first register and for storing the translated physical address in said second register and means for effecting initiation of said main memory by parallel readout of the content of said second register.   
     
     
       3. A virtual storage data processing system according to claim 1 wherein said common bus is shared by said job processor and file processor, each of said processors, when it accesses said main memory, using said common bus only in a transfer cycle of the virtual address and a receiving cycle of read data.   
     
     
       4. A virtual storage data processing system according to claim 1 wherein said job processor includes: (a) means having a cache memory for storing a partial copy of the data and instructions of said main memory and being accessible by a virtual address from said job processor, including: (i) an instruction cache for storing instructions from said main memory, and   (ii) a data cache for storing data read from said main memory;     (b) an instruction unit connected to said instruction cache for fetching and decoding an instruction word to be executed next from said instruction cache; and   (c) an execution unit connected to said instruction unit and said data cache for reading necessary data from said data cache in accordance with an instruction from said instruction unit to execute the instruction.   
     
     
       5. A virtual storage data processing system according to claim 4 wherein at least one of said instruction cache and data cache includes: (a) a data unit for retaining a partial copy of said main memory;   (b) a directory for retaining the virtual address of said main memory stored in said data unit;   (c) a valid indication unit for indicating validity of said virtual address;   (d) a latch register for latching the virtual address sent from said file processor;   (e) compare means for comparing the virtual address latched in said latch register with the virtual address retained in said directory; and clear means for clearing said valid indication unit in accordance with the result of said comparison operation.     
     
     
       6. A virtual storage data processing system according to claim 5 further comprising: a cache memory controller including means responsive to the content of said valid indication unit, in a read access operation, for reading the corresponding data if it is in said cache memory and send it back to the processor that requests the access or for sending a virtual address to said address translation unit if said data is not in said cache memory, while in a write access operation, for writing the corresponding data in said cache memory if it is in said cache memory and for writing said corresponding data in said main memory, or if said corresponding data is not in said cache memory, for writing said corresponding data in said main memory.   
     
     
       7. A virtual storage data processing system according to claim 6 wherein said cache memory controller includes means responsive to absence of the requested data from the main memory for clearing said valid indication unit for the data corresponding to the virtual address, and means responsive to absence of the data from the main memory in the write access operation for clearing the valid indicating unit for the corresponding data if the write data is in said cache memory. 
     
     
       8. A virtual storage data processing system according to claim 6 wherein said cache memory controller includes means responsive to absence of the corresponding data from the cache memory in the read access operation for issuing a memory initiation signal to said main memory and for setting a valid indication unit for the corresponding data, and means responsive to a page fault signal being received from said address translation unit for clearing the corresponding valid indication unit, said memory initiation signal being issued when the page fault signal is received from said address translation unit after issuing a memory request signal. 
     
     
       9. A virtual storage data processing system according to claim 8 wherein said cache memory controller includes means for setting said valid indication unit in the case of the read access to said main memory due to the fact that the corresponding data is not in said cache memory, and for clearing said valid indication unit in the case of the write access to said main memory from said file processor, in the order of memory access requests onto said common bus.