Drive circuit

Abstract

A drive circuit which can drive an IGFET in a non-saturated region over a long period time without reduction in level is disclosed. The drive circuit comprises a series circuit of a plurality of directional elements connected between a power supply terminal and an output terminal, a plurality of control terminals receiving repetitional signals and a plurality of capacitors coupled between the control terminals and intermediate junctions of the series circuit.

We claim: 
     
       1. A drive circuit comprising a first voltage generating circuit means connected between a first voltage terminal and a voltage output terminal, a second voltage generating circuit means connected between said first voltage terminal and said voltage output terminal, said first voltage generating circuit means having at least a first and a second transistor each operating as a rectification element and being connected in series, a first capacitor connected to a point between said first and second transistors, said second voltage generating circuit means having a third and a fourth transistor each operating as a rectification element and being connected in series, a second capacitor connected to a point between said third and fourth transistors, means for supplying a first clock signal to said first capacitor, means for supplying a second clock signal to said second capacitor, said second clock signal having a phase which is different from the phase of said first clock signal, and a fifth transistor connected between said voltage output terminal and a second voltage terminal for receiving an input signal, whereby an output voltage is derived from said voltage output terminal, when said fifth transistor is made nonconductive, said output voltage being smoothed by said first and second voltage generating circuit means. 
     
     
       2. The circuit according to claim 1, further comprising a sixth transistor for receiving said input signal, a seventh transistor for receiving said output voltage derived from said voltage output terminal, said sixth and seventh transistors being connected in series between said first voltage terminal and said second voltage terminal, and an eighth transistor connected between said first voltage terminal and said voltage output terminal. 
     
     
       3. A drive circuit comprising a first voltage terminal, first, second and third field effect transistors coupled in series between said first voltage terminal and a first node, each of said first, second and third transistors having a gate and a drain connected in common, a first clock terminal for receiving a first clock signal, a second clock terminal for receiving a second clock signal having a phase which is different from the phase of said first clock signal, a first capacitor connected between said first clock terminal and a connection point of said first and second transistors, a second capacitor connected between said second clock terminal and a connection point between said second and third transistors, a second voltage terminal, an input terminal for receiving an input signal, a fourth field effect transistor connected between said first node and said second voltage terminal and having a gate connected to said input terminal, a fifth transistor connected between said first voltage terminal and said first node, an output terminal, a sixth transistor connected between said output terminal and said second voltage terminal and having a gate connected to said input terminal, and a seventh transistor connected between said first voltage terminal and said output terminal and having a gate connected to said first node. 
     
     
       4. A drive circuit comprising a first voltage generating circuit, a second voltage generating circuit, each of said first and second voltage generating circuits generating output voltages having a larger value than a power source voltage at their output terminal, means for receiving an input signal, first clamp means for clamping the potential at the output terminal of said first voltage generating circuit to a reference voltage when said input signal is present, second clamp means for clamping the potential at the output terminal of said second voltage generating circuit to said reference voltage when said input signal is absent, and a first push-pull circuit controlled by the potentials of the output terminals of said first and second voltage generating circuits in a complementary manner. 
     
     
       5. The circuit according to claim 4, further comprising a second push-pull circuit controlled by the potentials of the output terminals of said first and second voltage generating circuits in such a manner that an output signal of said second push-pull circuit is opposite in phase to that of said first push-pull circuit. 
     
     
       6. The circuit according to claim 3, further comprising an acoustic tranducer having a first terminal coupled to the output terminal of said first push-pull circuit and a second terminal coupled to the output terminal of said second push-pull circuit. 
     
     
       7. The circuit according to claim 4, in which each of said voltage generating circuits includes a series circuit of directional elements coupled between a terminal receiving the power supply voltage and the output terminal thereof, a plurality of clock terminals for receiving clock signals and a plurality of capacitors coupled between said clock terminals and intermediate junctions of said directional elements.