Data processing system

Abstract

A data processing system in which a scan-in operation is initiated to scan in data for giving rise to occurrence of pseudo-failure in response to an address coincidence signal representative of a pseudo-failure signal. A one-shot suppression pulse signal is issued for inhibiting temporarily operation execution during a time span between the scan-in and the occurrence of failure.

What is claimed is: 
     
       1. A data processing system having a function of scanning-in pseudo-failure data so as to investigate the operating condition of the system comprising: operation executing means for executing operations while receiving a permission signal, including a plurality of flip-flops and means for producing a freeze signal when failure occurs in said operation executing means as indicated by a condition of at least one of said flip-flops;   scan control means for scanning-in said pseudo-failure data into said flip-flops in said operation executing means to produce a pseudo-failure condition therein and cause generation of said freeze signal;   operation control means for supplying said permission signal to said operation executing means and including means responding to said freeze signal for inhibiting application of said permission signal to said operation executing means so that said operation executing means is caused to pause in its operation; and   signal providing means responding to a signal ordering generation of said pseudo-failure condition for providing a one-shot scan-in request signal to said scan control means to start a scan-in operation of said pseudo-failure data and providing a one-shot suppression signal to cause operation of said inhibiting means in said operation control means, said one-shot suppression signal having a pulse width covering a time span extending until after a time point at which said operation executing means produces said freeze signal in response to said scan-in operation.   
     
     
       2. A data processing system according to claim 1, further comprising machine check controlling means for activating execution of a failure processing operation upon occurrence of failure in said operation executing means, wherein said operation executing means includes means for generating a machine check signal for activating said machine check control means in addition to said freeze signal when failure occurs in said operation executing means. 
     
     
       3. A data processing system according to claim 2, wherein said operation executing means includes arithmetic operation means and storage control means for controlling said arithmetic operation means in accordance with previously stored microinstructions, said arithmetic operation means and said storage control means each including means for producing, respectively, said freeze signal and said machine check signal upon occurrence of internal failure; means for supplying a clock signal to said operation executing means to control operation thereof;   said machine check control means including means for responding to said machine check signal by inhibiting said clock signal from being supplied to said operation executing means; means for logging out the outputs from flip-flops included in said operation executing means and said storage control means; reset means for resetting said flip-flops included in said operation executing means following said logging out operation; means for commanding said scan control means to scan a start address of said failure processing micro-instruction routine in said storage control means following said resetting operation; means for clearing inhibition of supply of said clock signal following said scan-in operation of said start address; and execution initiating request means for issuing a request signal for initiation of execution of operation following said clearing of inhibition operation; and   said operation control means including a first flip-flop which is set to a first state by a reset signal outputted from said reset means and responds to said execution initiating request signal to be set to a second state in response to a start signal supplied externally; and said inhibiting means comprises means for producing a signal to inhibit operation of said operation executing means in response to said freeze signal, said suppression signal or an output signal produced by said first flip-flop when said first flip-flop is in said first state.   
     
     
       4. A data processing system according to claim 3, wherein said inhibiting means includes an OR gate having inputs supplied with said freeze signal, said suppression signal and said output signal produced from said first flip-flop in said first state; a second flip-flop for storing therein the output signal from said OR gate in response to a first clock signal utilized for controlling said operation executing means and producing as the output signal said inhibit signal which is supplied to said arithmetic operation means; and fourth means having inputs supplied with the output signal from said second flip-flop and said start signal for applying an operation inhibiting signal to said control storage means during a given time span except for the time in which said second flip-flop does not output said inhibit signal or said start signal is being inputted. 
     
     
       5. A data processing system according to claim 2, wherein said operation control means includes an OR gate having inputs supplied with said freeze signal and said suppression signal, and a flip-flop for storing an output signal from said OR gate in response to a clock signal utilized for controlling operation of said operation executing means and for sending out a signal commanding said inhibition; said machine check control means including means for inhibiting supply of said clock signal in response to said machine check signal. 
     
     
       6. A data processing system according to one of claims 3 or 4, including means for issuing said ordering signal when an address portion of the instruction coincides with a predetermined address. 
     
     
       7. A data processing system according to claim 1, wherein said signal providing means includes a flip-flop which responds to a first clock signal having a longer period than a second clock signal for controlling said operation executing means. 
     
     
       8. A date processing system according to claim 7, wherein said signal providing means includes a first flip-flop which is set by said ordering signal; a second flip-flop for storing the output of said first flip-flop in response to said second clock signal; a third flip-flop responding to a third clock signal which has the same period as that of said first clock signal and is out of phase with said first clock signal by half of said period, said third flip-flop producing an output signal to reset said first flip-flop; and an OR gate having inputs supplied with output signals from said first, second and third flip-flops for producing as an output said inhibiting signal. 
     
     
       9. A data processing system according to claim 8, wherein said scan control means comprises means for performing said scan-in operation in response to an output signal from an AND gate which has inputs supplied with the output from said second flip-flop and an inverted output of said third flip-flop. 
     
     
       10. A data processing system according to one of claims 7 to 9, wherein said operation control means includes an OR gate having inputs supplied with said freeze signal and said suppression signal, and a flip-flop for storing the output of said OR gate in response to said first clock signal and for producing said inhibition commanding signal.