P
US4493082AExpiredUtilityPatentIndex 89

Soft decision convolutional code transmission systems

Assignee: PLESSEY OVERSEASPriority: Nov 14, 1980Filed: Nov 13, 1981Granted: Jan 8, 1985
Est. expiryNov 14, 2000(expired)· nominal 20-yr term from priority
Inventors:CUMBERTON JOHNFOSTER ALUN ERAE ALEXANDER SFERNANDES VERNON JCARTER MICHAEL R
H04L 27/3872H04L 27/34H04L 1/0054H04L 25/067H04L 27/3433H03M 13/41H04L 1/0059
89
PatentIndex Score
68
Cited by
5
References
12
Claims

Abstract

A data transmission system in which data is transmitted in a form incorporating additional data providing for error correction at the receiver. The data is encoded in a transmitter using a signal mapping system which maps a number of original digits and also digits produced by a convolutional encoder. The data at the receiver is decoded using hard and soft decision decoding which can correct errors in the received data.

Claims

exact text as granted — not AI-modified
What we claim is: 
     
       1. A transmission system for the transmission of data or digitized analogue information from a transmitter to a receiver including a transmitter containing a convolutional encoder and a signal mapping device connected thereto to produce a two dimensional coded output signal, and including a receiver containing a convolutional decoder with soft decision decoding, connected to a reverse mapping means to produce output data, said transmitter including a serial-to-parallel converter producing n binary outputs only one of which is fed to the convolutional encoder which produces two binary output bits which are combined with the n-1 remaining bits and fed to the signal mapping device to produce the two dimensional coded output signal, the n-1 bits defining a square within a grid, within which square the two bits produced by the convolutional encoder define the position of the signals to be transmitted. 
     
     
       2. A transmission system as claimed in claim 1, in which data is transmitted between the transmitter and the receiver at n/(n+1) of the rate of the data incoming to the transmitter when the proposed redundant coding system is not used. 
     
     
       3. A transmission system as claimed in claim 2 in which the signals to be transmitted produced by the signal mapping device comprise four-bit in-phase co-ordinates fed to the I channel of a modulator and four-bit quadrature-phase co-ordinates which are fed to the Q channel of the modulator, the output of the modulator being the output of the transmitter. 
     
     
       4. A transmission system as claimed in claim 1 in which the receiver further includes an analogue to digital converter which produces from the input signal, a stream of parallel input binary digits, in which the convolutional decoder includes a Viterbi algorithm decoder operating on a number of the parallel input binary digits to produce binary digits analogous to the binary digits produced by the convolutional encoder in the transmitter. 
     
     
       5. A transmission system as claimed in claim 4 in which the output binary digits from the Viterbi algorithm decoder are combined with the remaining binary digits from the analogue to digital converter and are fed to the input of a requantiser which is responsive to the input binary digits to determine the most likely set of co-ordinates for each transmitted point of the two dimensional coded signal. 
     
     
       6. A transmission system as claimed in claim 5 in which the information is stored in two circular lists of length L for each of the four nodes, one storing successive origins and one storing corresponding transitions. 
     
     
       7. A transmission system as claimed in claim 6 in which the information relating to the trellis diagram is stored in such a manner that desired output information can be obtained by tracing a path back through the memory without any requirement for transferring all of the relevant memory contents. 
     
     
       8. A transmission system as claimed in claim 6 in which the information in the form of lists is stored in respective shift registers or their equivalents and in which the beginning and end of each equivalent shift register is marked by a pointer address which is incremented once for every shift of the shift register and in which to avoid using memory locations whose addresses increment indefinitely, the pointer address is incremented modulo L (=2 N ) so that all memory locations are contained in a list of size L such that the same address can be used to extract information. 
     
     
       9. A transmission system as claimed in claim 5 including a phase ambiguity detector and corrector connected to the requantiser which uses the output binary digits from the Viterbi algorithm detector to derive a false transition rate on the trellis diagram, and when a threshold error rate is exceeded rotates the incoming signals. 
     
     
       10. A transmission system as claimed in claim 9 in which the phase ambiguity detector discriminates between false transitions caused by noise or by phase ambiguity by using a distance measurement of the received point from a given mapping point. 
     
     
       11. A data modem including a transmitter and a receiver as defined in any one of claims 1, 2, 3, 4, 5, 6, 7, 8, 9, or 12. 
     
     
       12. A data modem including a transmitter and a receiver as defined in claim 2.

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