Bootstrapped level shift interface circuit with fast rise and fall times

Abstract

An input circuit for a field effect transistor (FET) storage is described which consists of a bootstrap inverter which by a dynamically operating charge-up circuit is supplemented for charging up the bootstrap node to the full operating voltage, and which can be directly controlled with TTL levels without a level converter consisting of bipolar transistors being inserted. For that purpose, the input electrode of the bootstrap capacitor of the dynamically operating charge-up circuit is connected to the output of an inverter following the input circuit. Furthermore a discharge branch is provided for the node of the dynamically operating charge-up circuit. With its other end, together with the gate of the charge-up field effect transistor of the dynamic charge-up circuit, the discharge branch is connected to the output of another inverter following the first one. It is thus assured that when owing to the bootstrap effect the potential of the bootstrap node rises over the value VH of the operating voltage, this node cannot be discharged via the FET's in the charge-up circuit to the positive pole of the operating voltage source. This would counteract the rise of the potential of the bootstrap node so that the potential and the output of the input circuit would rise only slowly, and would not reach the full value VH of the operating voltage.

What is claimed is: 
     
       1. In an input circuit having an input node and an output node, for a monolithically integrated semiconductor storage of field effect transistors, which input circiut is controlled with low signal levels applied to its input node and which input circuit for level conversion uses bootstrap means, and which input circuit contains a dynamically operating charge-up circuit for charging up a bootstrapping node of the bootstrap means to the operating voltage, the improvement in the charge-up circuit comprises: a coupling capacitor having an input node and an output node;   a first inverter having its input connected to the output node of the input circuit and its output connected to the input node of the coupling capacitor;   first and second FET's, the gate of the first FET and the source of the second FET being connected to the output node of said coupling capacitor, the drain of said first and second FET's being connected in common to a voltage source;   a discharge circuit having one end connected to the output node of the coupling capacitor, the opposite end of the discharge circuit being connected to the gate of the second FET;   a second inverter having its input connected to the output of the first inverter and its output connected to the gate of the second FET;   said first FET having its source connected to the said bootstrapping node of the bootstrap means, whereby the charge-up circuit causes the bootstrap means to be maintained at full operating voltage.   
     
     
       2. A circuit as claimed in claim 1, wherein the discharge circuit comprises a series connection of a plurality of FET's, the first of which is connected to the output node of said coupling capacitor and is maintained continuously conductive, the other of said plurality of FET's being at least one load FET, with its gate electrode being connected to its drain electrode, its source electrode being connected to the gate of said second FET. 
     
     
       3. A circuit as in claim 1 or 2, wherein the input circuit comprises an inverter. 
     
     
       4. A circuit as in claim 1 or 2, wherein the input circuit comprises a non-inverting buffer. 
     
     
       5. A circuit as in claim 1 or 2, wherein the FET's are N-channel. 
     
     
       6. A circuit as in claim 1 or 2, wherein the FET's are P-channel.