Circuit to minimize local clock frequency disturbances when phase locking to a reference clock circuit

Abstract

A frequency disturbance minimization circuit for use in a phase locked loop circuit. A pulse generator eliminates random phase shift, which occurs after a reference clock outage, by synchronizing counted down derivatives of the local and reference clock circuits. A window circuit provides a signal representative of the difference in phase between these local and reference clock circuits. A counter accumulates these phase difference window signals for periodic interrogation by a microprocessor which causes a voltage controlled oscillator to adjust its frequency in the direction necessary to eliminate this phase difference.

What is claimed is: 
     
       1. A clock signal phase locking arrangement for use in a switching system which includes a source of reference clock signals, said phase locking arrangement comprising: a control circuit operative to provide a plurality of local clock frequency control signals, said control circuit being connected to said reference clock signal source and further operative in response to an absence of said reference clock signals for a predetermined time to maintain the local clock frequency control signal in its current state;   a local clock circuit connected to said control circuit and operative in response to said plurality of local clock frequency control signals to provide a plurality of local clock signals, each having a frequency associated with a different one of said control signals;   said control circuit being further operative in response to detection of said reference clock signals after said absence to generate first and second synchronization signals;   a first frequency divider connected to said source of reference clock signals and said control circuit, and operative in response to said first synchronization signal to provide counted down reference clock signals of a characteristic frequency;   a second frequency divider connected to said local clock circuit and said control circuit, and operative in response to said second synchronization signal to provide counted down local clock signals of said characteristic frequency; and   a phase difference measurement circuit, connected to said first and second frequency dividers, and said control circuit, and operative in response to said counted down reference clock signals and said counted down local clock signals to provide a phase difference signal representative of the phase difference between each of said counted down reference clock signals and an associated one of said counted down local clock signals;   said control circuit being further operative in response to each of said phase difference signals to provide an associated one of said control signals of a characteristic representative of the duration of said phase difference signal, whereby the frequency of said local clock circuit is adjusted to eliminate the difference in phase between said counted down local clock signals and said counted down reference clock signals.   
     
     
       2. A phase locking arrangement as claimed in claim 1, wherein said local clock circuit comprises: a voltage controlled oscillator.   
     
     
       3. A phase locking arrangement as claimed in claim 1, wherein said first frequency divider is initialized to a predetermined count in response to said synchronization signal. 
     
     
       4. A phase locking arrangement as claimed in claim 1, wherein said second frequency divider is initialized to a predetermined count in response to said synchronization signal. 
     
     
       5. A phase locking circuit as claimed in claim 1, wherein said phase difference measurement circuit comprises: a first timing circuit connected to said first frequency divider and operative in response to said counted down reference clock signals to provide a phase window initiation signal;   a second timing circuit connected to said second frequency divider and operative in response to said counted down local clock signals to provide a phase window termination signal;   signalling means connected to said first and second timing circuits and operative in response to said phase window initiation signal to provide the leading edge of said phase difference signal and further operative in response to said phase window termination signal to provide the trailing edge of said phase difference signal.   
     
     
       6. A phase locking circuit as claimed in claim 5, wherein a source of trigger signals is further included and said first timing circuit comprises: a first storage means connected to said first frequency divider and said trigger signal source, and operative in response to said counted down reference clock signal and a first trigger signal to provide a first storage signal;   second storage means connected to said first storage means and said trigger signal source, and operative in response to said first storage signal and a second trigger signal to provide a second storage signal; and   first gating means connected to said first and second storage means ad operative in response to said first and second storage signals to provide said phase window initiation signal.   
     
     
       7. A phase locking circuit as claimed in claim 6, wherein said first storage means comprises a D-type flip-flop. 
     
     
       8. A phase locking circuit as claimed in claim 7, wherein said first storage means further comprises a delay circuit connected to said D-type flip-flop. 
     
     
       9. A phase locking circuit as claimed in claim 8, wherein said delay circuit comprises a pair of series connected inverters. 
     
     
       10. A phase locking circuit as claimed in claim 6, wherein said second storage means comprises a D-type flip-flop. 
     
     
       11. A phase locking circuit as claimed in claim 5, wherein a source of trigger signals is further included and said second timing circuit comprises: first storage means connected to said second frequency divider and said trigger signal source, and operative in response to said counted down local clock signal and a first trigger signal to provide a first storage signal;   second storage means connected to said first storage means and said trigger signal source and operative in response to an absence of said first storage signal to provide a second storage signal;   first gating means connected to said first and second storage means, and operative in response to said first and second storage signals to provide the leading edge of said phase window termination signal;   said second storage means being further operative in response to said first storage signal and a second trigger signal to provide a third storage signal;   said first gating means being further operative in response to said first and third storage signals to provide the trailing edge of said phase window termination signal.   
     
     
       12. A phase locking circuit as claimed in claim 5, wherein a source of trigger signals is further included and said second timing circuit comprises: first storage means connected to said second frequency divider and said trigger signal source, and operative in response to said counted down local clock signal and a first trigger signal to provide a first storage signal;   second storage means connected to said first storage means and said trigger signal source, and operative in response to said first storage signal and a second trigger signal to provide a second storage signal;   first gating means connected to said first and second storage means and operative in response to said first and second storage signals to provide a first gating signal;   third storage means connected to said first gating means and said trigger signal source, and operative in response to said first gating signal and a third trigger signal to provide a third storage signal;   fourth storage means connected to said third storage means and said trigger signal source and operative in response to an absence of said third storage signal to provide a fourth storage signal; and   second gating means connected to said third and fourth storage means and operative in response to said third and fourth storage signals to provide the leading edge of said phase window termination signal;   said fourth storage means being further operative in response to said third storage signal and a fourth trigger signal to provide a fifth storage signal;   said second gating means being further operative in response to said third and fifth storage signals to provide the trailing edge of said phase window termination signal.   
     
     
       13. A phase locking circuit as claimed in claim 12, wherein said first storage means comprises a D-type flip-flop. 
     
     
       14. A phase locking circuit as claimed in claim 13, wherein said first storage means further comprises a delay circuit connected to said D-type flip-flop. 
     
     
       15. A phase locking circuit as claimed in claim 14, wherein said delay circuit comprises a pair of inverters. 
     
     
       16. A phase locking circuit as claimed in claim 13, wherein said first storage means further comprises an inverter connected between said D-type flip-flop and said second frequency divider. 
     
     
       17. A phase locking circuit as claimed in claim 12, wherein said second storage means comprises a D-type flip-flop. 
     
     
       18. A phase locking circuit as claimed in claim 12, wherein said third storage means comprises a D-type flip-flop. 
     
     
       19. A phase locking circuit as claimed in claim 12, wherein said fourth storage means comprises a D-type flip-flop. 
     
     
       20. A phase locking circuit as claimed in claim 12, wherein said fourth storage means further comprises a delay circuit connected between said third and fourth storage means. 
     
     
       21. A phase locking circuit as claimed in claim 20, wherein said delay circuit comprises a pair of inverters. 
     
     
       22. A phase locking circuit as claimed in claim 5, wherein said signalling means comprises a storage circuit. 
     
     
       23. A phase locking circuit as claimed in claim 22, wherein said storage circuit comprises a D-type flip-flop having a clock input connected to said first timing circuit and a clear input connected to said second timing circuit. 
     
     
       24. A phase locking circuit as claimed in claim 6, wherein said source of trigger signals comprises a voltage controlled oscillator and a third frequency divider connected to said oscillator. 
     
     
       25. A phase locking circuit as claimed in claim 12, wherein said source of trigger signals comprises a voltage controlled oscillator and a third frequency divider connected to said oscillator. 
     
     
       26. A phase locking circuit as claimed in claim 1, wherein said control circuit comprises: a source of trigger signals and a counter connected to both said phase difference measurement circuit and said source of trigger signals;   said counter being operative to count said trigger signals for the duration of each of a predetermined number of phase difference signals and to provide a number representative of the total number of such trigger signals counted;   a microprocessor connected to said counter and said local clock circuit and operative in response to a predetermined number of local clock signals equal to said predetermined number of phase difference signals, to retrieve said number from said counter and to determine the average number of trigger signals counted for each phase difference signal;   said microprocessor being further operative in response to said average number being above or below a predetermined threshold to provide an associated positive or negative number; and   a digital-to-analog converter connected to said microprocessor and operative in response to each of said positive and negative numbers to provide an associated local clock frequency control signal.   
     
     
       27. A phase locking circuit as claimed in claim 1, wherein said control circuit comprises: pulse detection means connected to said source of reference clock signals, and operative in response to detection of said reference clock signals to provide a reference clock detected signal, and further operative in response to detection of an absence of said reference clock signals for said predetermined time to provide a reference clock failure signal;   processing means connected to said pulse detection means and operative in response to said reference clock failure signal to maintain the local clock frequency control signal in its current state;   said processing means being further operative in response to said reference clock detected signal to provide an enable signal; and   pulse generating means connected to said processing means, said local clock circuit and said source of reference clock signals, and operative in response to said enable signal and said reference clock signals to provide said first synchronization signal, and further operative in response to said enable signal and said local clock signals to provide said second synchronization signal.   
     
     
       28. A phase locking circuit as claimed in claim 27, wherein said pulse detection means comprises a retriggerable monostable multivibrator. 
     
     
       29. A phase locking circuit as claimed in claim 27, wherein said pulse generating means comprises: a first D-type flip-flop having a first output, a first data input and a first clock input, said first data input being connected to said processing means, said first clock input being connected to said source of reference clock signals, and said first output being connected to said first frequency divider; and   a second D-type flip-flop having a second output, a second data input and a second clock input, said second data input being connected to said processing means, said second clock input being connected to said local clock circuit, and said second output being connected to said second frequency divider.   
     
     
       30. A phase locking circuit as claimed in claim 29, wherein a first inverter is included between said source of reference clock signals and said first clock input and a second inverter is included between said local clock circuit and said second clock input.