Self initializing phase locked loop ring communications system

Abstract

A communications network including a plurality of terminals coupled together to provide a unidirectional communications ring. Each of the terminals is coupled in series along the ring. Each terminal is adapted to transmit (at an associated data rate) a digital signal to the next downstream terminal on the ring. Each terminal is adapted to receive a digital signal at the data rate associated with the next upstream terminal. The received digital signal is applied to a phase locked loop characterized by a hold time which exceeds its lock time. The phase locked loop extracts a local timing signal for re-clocking the received digital signal. The transmission time of N bits is less than the hold time of the phase locked loop. Each terminal monitors the re-clocked signal to identify when same valued consecutive bits are received for a period less than the phase locked loop hold time, and upon such detection to cause that terminal to generate at least one transition.

What is claimed is: 
     
       1. A ring communications system comprising a plurality of terminals coupled together to provide a unidirectional communications ring, each of said terminals comprising: A. means for transmitting digital signals at a transmit data rate (1/T) associated with said terminal to the next downstream terminal, said transmitting means being operative in a first state to transmit run length limited digital signals having fewer than N consecutive bits having the same value, and operative in a second state to transmit digital signals having N+A consecutive bits having the same binary value, followed by at least one bit having the other binary value,   B. means for receiving digital signals from the next upstream terminal, said receiving means including: i. a phase locked loop (PLL) means for generating a receive (Rx) clock signal from said received digital signal, said PLL means including a phase locked loop having a characteristic hold time (H) exceeding its characteristic lock time (L) and where (N+A)×T is less than H,   ii. shift register means for re-clocking said received digital signals in response to said Rx clock signal     C. control means for detecting signal level transitions in said re-clocked digital signals, and means operative when N consecutive bits of said re-clocked digital signals have the same value, for controlling said transmitting means to be in its second state for a period equal to (N+A+M)×T, where M is greater than or equal to 1, and A is greater than or equal to 0, and for controlling said transmitting means to be in its first state otherwise.   
     
     
       2. A ring communications system according to claim 1 further comprising means for maintaining said transmit data rates the same from terminal to terminal. 
     
     
       3. A ring communications system according to claim 1 further comprising means for establishing said transmit data rates whereby said transmit data rates may vary independently from terminal to terminal. 
     
     
       4. A ring communications system according to claims 1 or 2 or 3 where M×T is greater than or equal to L and wherein said transmitting means is further operative in said second state following said transmission of N+A consecutive same value bits to transmit M consecutive bits having a pattern of values characterized by a time-density of signal level transitions above a predetermined threshold. 
     
     
       5. A ring communications system according to claim 4 wherein said transmit means includes means for establishing said bit pattern to be a succession of alternating values. 
     
     
       6. A ring communications system according to claims 1 or 2 or 3 wherein said phase locked loop includes: A. means for generating P clock signals at said frequency f o , each of said P clock signals being shifted in phase by 1/P cycles with respect to another of said P clock signals,   B. controllable clock selector means for selecting one of said P clock signals as said Rx clock signal,   C. a first phase detector including means for generating first error signal representative of the relative phase shift between said received digital signals and the one of said P clock signals shifted in phase +1/P cycles with respect to said Rx clock signal,   D. a second phase detector including means for generating a second error signal representative of the relative phase shift between said received digital signals and the one of said P clock signals shifted in phase by -1/P cycles with respect to said Rx clock signal,   E. controller means responsive to said first and second error signals for controlling said clock selector: when said first error signal becomes greater than a predetermined threshold, to select as said Rx clock signal the one of said P clock signals shifted in phase by +1/P cycles with respect to the previously selected Rx clock signal, and   when said second error signal becomes greater than a predetermined threshold, to select the one of said P clock signals shifted in phase by -1/P cycles with respect to the previously selected Rx clock signal.     
     
     
       7. A ring communications system according to claim 4 wherein said phase locked loop includes: A. means for generating P clock signals at said frequency f o , each of said P clock signals being shifted in phase by 1/P cycles with respect to another of said P clock signals,   B. controllable clock selector means for selecting one of said P clock signals as said Rx clock signal,   C. a first phase detector including means for generating first error signal representative of the relative phase shift between said received digital signals and the one of said P clock signals shifted in phase +1/P cycles with respect to said Rx clock signal,   D. a second phase detector including means for generating a second error signal representative of the relative phase shift between said received digital signals and the one of said P clock signals shifted in phase by +1/P cycles with respect to said Rx clock signal,   E. controller means responsive to said first and second error signals for controlling said clock selector: when said first error signal becomes greater than a predetermined threshold, to select as said Rx clock signal the one of said P clock signals shifted in phase by +1/P cycles with respect to the previously selected Rx clock signal, and   when said second error signal becomes greater than a predetermined threshold, to select the one of said P clock signals shifted in phase by -1/P cycles with respect to the previously selected Rx clock signal.     
     
     
       8. A ring communications system according to claims 1 or 2 or 3 wherein said phase locked loop includes: a clock generator having a characteristic operating frequency for outputting said Rx clock signal,   means for receiving said received digital signal,   means for comparing the phase of said received digital signal and said Rx clock signal, and   phase selection means responsive to said phase comparison means for discretely changing the relative phase difference between said received digital signal and said clock signal when said phase difference exceeds a predetermined threshold.   
     
     
       9. A ring communications system according to claim 8 wherein said clock generator comprises means for selectively outputting, in response to said phase selection means, a clock signal having one of a plurality of discrete phases.