Interface for managing information exchanges on a communications bus

Abstract

An interface for managing information exchanges on a communications bus between at least one control unit and peripheral units, or between said peripheral units. The exchanged information includes data and a destination address of said data. The interface is characterized in that it comprises for each unit, data transmission circuitry connected to the unit and to the bus for managing the data transmission on the bus to the unit having the destination address, data reception circuitry connected to the units and to the bus, for managing the reception of data by the unit having the destination address, and management circuitry for managing the addressing of the units during exchanges and in particular for managing access priorities to the bus, without necessitating the intervention of the control unit. This interface can be used for information exchanges between processing or measuring units.

What is claimed is: 
     
       1. An interface arrangement for managing the exchange of information between units connected by a communications bus, said units including at least one control unit and a plurality of peripheral units, each of said units having a distinct address, any one of said units being capable of transmitting and receiving information comprising data and a destination address, said destination address corresponding to the address of the one of said units which receives transmitted information wherein said interface arrangement comprises: (a) a plurality of data reception means, each of said data reception means being connected to receive information from said communications bus and to transmit information to an associated one of said units;   (b) a plurality of data transmission means, each of said data transmission means being connected to transmit information to said communications bus and to receive information from said associated one of said units;   (c) scanning means for generating address signals in a predetermined sequence, said scanning means being connected to transmit said address signals to said communications bus, said address signals representing the addresses of said units and said predetermined sequence corresponding to the order of priority of said units for access to said communications bus by said units;   (d) a plurality of priority comparison means, each of said priority comparison means being connected to receive said address signals from said communications bus and to transmit control signals to an associated one of said data transmission means; and   (e) a plurality of destination address comparison means, each of said destination address comparison means being connected to receive destination address signals from said communications bus and to transmit control signals to an associated one of said data reception means,   wherein each of said priority comparison means compares said address signals generated by said scanning means with signals representing the address of an associated unit and generates an equality signal in response to correspondence, each of said destination address comparison means compares destination address signals received from said communications bus with signals representing the address of an associated unit and generates an equality signal in response to correspondence, each of said priority comparison means in which said equality signal was not generated being disabled from transmitting a data transmission enabling signal to said associated data transmisssion means and each of said destination address comparison means in which said equality signal was not generated being disabled from transmitting a data reception enabling signal to said associated data reception means.   
     
     
       2. The interface arrangement as defined in claim 1, wherein said scanning means is adjustable and programmable. 
     
     
       3. The interface arrangement as defined in claim 1, wherein each of said priority comparison means is operatively connected to said bus whereby a signal indicating the transmission of data to said bus by said associated data transmission means is transmitted to said bus in response to the transmission of said data transmission enabling signal by said priority comparison means, and wherein each of said destination address comparison means is operatively connected to said bus whereby a signal indicating the reception of data from said bus by said associated data reception means is transmitted to said bus in response to the transmission of said data reception enabling signal by said destination address comparison means. 
     
     
       4. The interface arrangement as defined in claim 1, wherein each of said data transmission means comprises a data transmission buffer register and an address transmission buffer register, each of said transmission buffer registers being connected to transmit information to said bus and to receive information from said associated unit. 
     
     
       5. The interface arrangement as defined in claim 1, wherein each of said data reception means comprises a data reception buffer register and an address reception buffer register, each of said reception buffer registers being connnected to receive information from said bus and to transmit information to said associated unit. 
     
     
       6. The interface arrangement as defined in claim 1, further comprising a plurality of transmission management logic circuits, each of said transmission management logic circuits being connected to transmit a signal to an associated data transmission means for enabling the transmission of information from an associated unit to said associated data transmission means and to transmit a signal to an associated priority comparison means for indicating the transmission of said information to said associated data transmission means. 
     
     
       7. The interface arrangement as defined in claim 1, further comprising a plurality of reception management logic circuits, each of said reception management logic circuits being connected to transmit a signal to an associated destination address comparison means for indicating the readiness to receive information from an associated data reception means and to transmit a signal to said associated data reception means for enabling the transmission of information from said associated data reception means to an associated unit. 
     
     
       8. The interface arrangement as defined in claim 6, wherein each of said priority comparison means comprises an address comparator connected to said bus and to said associated unit for comparing said address signals generated by said scanning means with signals representing the address of said associated unit and outputting a signal representing equality in response to correspondence of said address signals, and a priority comparison logic circuit connected to receive said equality signal from said address comparator and said signal from an associated transmission management logic circuit for indicating the transmission of said information from said associated unit to said associated data transmission means, in response to which signals said priority comparison logic circuit outputs said data transmission enabling signal to said associated data transmission means. 
     
     
       9. The interface arrangement as defined in claim 7, wherein each of said destination address comparison means comprises an address comparator connected to said bus and to said associated unit for comparing said destination address signals generated by a unit different from said associated unit with signals representing the address of said associated unit and outputting a signal representing equality in response to correspondence of said address signals, and a destination address comparison logic circuit connected to receive said equality signal from said address comparator, said signal from said bus for indicating the transmission of data to said bus by said associated data transmission means, and said signal from an associated reception management logic circuit for indicating the reddiness to receive of said associated data reception means, in response to which signals said destination address comparison logic circuit outputs said data reception enabling signal to said associated data reception means. 
     
     
       10. The interface arrangement as defined in claim 8, wherein said priority comparison logic circuit comprises a D-type flip-flop. 
     
     
       11. The interface arrangement as defined in claim 9, wherein said destination address comparison logic circuit comprises a D-type flip-flop. 
     
     
       12. The interface arrangement as defined in claim 21, wherein said bus comprises a plurality of priority determination address lines, and said scanning means comprises a counting means connected to output said address signals to said plurality of priority determination address lines and a clocking means connected to output clocking signals to said counting means, wherein each of said predetermined sequence of address signals comprises a plurality of binary signals representing the increasing count carried out by said counting means. 
     
     
       13. The interface arrangement as defined in claim 12, wherein said scanning means further comprises a switching means, and said counting means has a plurality of output terminals for transmitting said binary signals and a reset terminal for receiving a reset signal, said switching means connecting said output terminals to said reset terminal such that said count is restarted in response to said count attaining a predetermined number, said predetermined number being adjustable by operation of said switching means. 
     
     
       14. The interface arrangement as defined in claim 12, wherein said scanning means further comprises a comparison means, and said counting means has a plurality of output terminals for transmitting said binary signals and a reset terminal for receiving a reset signal, said comparison means having a first plurality of input terminals for receiving binary signals representing a predetermined number, a second plurality of input terminals connected to said output terminals of said counting means, and an output terminal for outputting an equality signal in response to the equality of the binary signals received on said first and second pluralities of output terminals respectively, said output terminal of said comparison means being operatively connected to said reset terminal of said counting means such that said count is restarted in response to said count attaining said predetermined number, said predetermined number being adjustable. 
     
     
       15. The interface arrangement as defined in claim 14, wherein said reset terminal of said counting means is operatively connected to said bus such that said count is restarted in response to receipt of an interruption signal from said bus. 
     
     
       16. The interface arrangement as defined in claim 1, wherein said scanning means comprises interruption means connected to said bus such that the generation of said predetermined sequence of address signals is restarted in response to receipt of an interruption signal from said bus. 
     
     
       17. The interface arrangement as defined in claim 15, wherein said scanning means further comprises means for adjustably setting the number at which said count is restarted in response to said interruption signal. 
     
     
       18. The interface arrangement as defined in claim 5, wherein said address reception buffer register is connected to receive said address signals from said scanning means. 
     
     
       19. The interface arrangement as defined in claim 1, wherein said bus comprises a plurality of electrical conductors. 
     
     
       20. The interface arrangement as defined in claim 1, further comprising optoelectronic transducing means connecting said bus to said interface arrangement, wherein said bus comprises a plurality of optical transmission lines.