Smoothing circuit for display apparatus

Abstract

A desired character mainly composed of standard width dots selected from a matrix of orthogonally disposed rows and columns is displayed on a screen during scanning of the screen in horizontal and vertical directions. The display is smoothed by a circuit responsive to data stored in a memory. The smoothing involves the selected addition or removal, to or from particular portions of the character, of a small dot having a width one-third of the standard dot width.

What is claimed is: 
     
       1. A smoothing circuit for a display apparatus in which a desired character composed of selected standard width dots of a matrix of orthogonally disposed rows and columns thereof is displayed on a screen during scanning of the latter in horizontal and vertical directions; comprising: memory means for memorizing data R(t n-1 ), R(t n ), R(t n+1 ), D(t n-1 ), D(t n ) and D(t n+1 ), in which D represents data indicating the presence or absence of a dot in a row of said matrix being currently displayed, (t n ) represents a time interval corresponding to the horizontal scanning of a space being considered in a given one of said rows and which has a width equal to that of each of said dots, (t n-1 ) and (t n+1 ) are equivalent time intervals immediately preceding and following, respectively, said time interval (t n ), and R represents data indicating the presence or absence of a dot in a row of said matrix which is immediately adjacent to said row being currently displayed;   logical operation circuit means responsive to said data memorized in said memory means for performing logical operations thereon which satisify predetermined conditions so as to selectively alter said data D(t n ) in correspondence with the addition or removal, in said space being considered, of a small dot having a width one-third of said standard width, said predetermined conditions satisfied by said logical operations being as follows:   (a) The condition for altering said data D(t n ) in correspondence with the addition of said small dot in the front third of said space being considered is   R(t.sub.n-1)·R(t.sub.n)·D(t.sub.n-1)=1       (b) The condition for altering said data D(t n ) in correspondence with the addition of said small dot in the rear third of said space being considered is   R(t.sub.n)·R(t.sub.n+1)·D(t.sub.n+1)=1       (c) The condition for altering said data D(t n ) in correspondence with the removal of said small dot from the front third of a standard width dot in said space being considered is   R(t.sub.n-1)·R(t.sub.n)·R(t.sub.n+1)·D(t.sub.n-1)·D(t.sub.n+1)=1     and     (d) The condition for altering said data D(t n ) in correspondence with the removal of said small dot from the rear third of a standard width dot in said space being considered is   R(t.sub.n-1)·R(t.sub.n)·R(t.sub.n+1)·D(t.sub.-1)·D(t.sub.n+1)=1;     and     means for displaying on said screen said desired character as modified in accordance with said selectively altered data so that the displayed character has relatively smooth contours.   
     
     
       2. A smoothing circuit according to claim 1; in which said character is displayed in alternately occurring odd- and even-numbered fields, and said data R refers to the row of said matrix which immediately precedes said row being presently displayed during each said odd-numbered field and which immediately follows said row being presently displayed during each said even-numbered field. 
     
     
       3. A smoothing circuit according to claim 2; in which said screen is included in a cathode ray tube; and further comprising means responsive to said selectively altered data for generating a luminance signal for said cathode ray tube. 
     
     
       4. A smoothing circuit according to claim 1; in which said memory means includes a character memory having addresses corresponding to said rows and columns of said matrix, and register means for receiving said data R(t n-1 ), R(t n ), R(t n+1 ), D(t n-1 ), D(t n ) and D(t n+1 ) from said character memory. 
     
     
       5. A smoothing circuit according to claim 4; in which said logical operation circuit means includes pulse generating means providing first and second pulses at the front and rear thirds, respectively, of each said space being considered, decoding means receiving said first and second pulses and said data R(t n-1 ), R(t n ), R(t n+1 ), D(t n-1 ) and D(t n+1 ) from said register means and providing respective predetermined outputs therefrom, and logic elements receiving said outputs from said decoding means and said data D(t n ) from said register means for providing said selectively altered data therefrom.