Circuit for the protection of IGFETs from overvoltage

Abstract

A pair of IGFETs connected in cascade across a d-c power supply form a source/drain junction constituting the output terminal of a self-biasing amplifier to which binary-coded bipolar signals are transmitted by way of a voltage divider effectively inserted between an input terminal and the afore-mentioned junction, a tap of that voltage divider being connected to the gate of a first of these IGFETs whose source is tied to one of the two supply terminals; the drain and the gate of the second IGFET are tied to the opposite supply terminal. A protective diode lies between the input terminal and the supply terminal connected to the source of the first IGFET so as to be reverse-biased by the voltage divider in a quiescent state and to break down in the presence of an abnormally high input voltage of a given polarity (positive in the specific instance described). An ancillary IGFET connected between the input terminal and the opposite supply terminal has its gate biased at a potential so chosen that this IGFET conducts in the presence of an input voltage of the other (negative) polarity approaching the forward-conduction threshold of the protective diode so as to prevent that threshold from being reached. The voltage divider may terminate at a source/drain junction of another pair of cascaded IGFETs that are identical with the IGFETs of the first pair and are connected in parallel therewith across the supply, the gate of the first IGFET of this other pair being tied to the last-mentioned source/drain junction which is also connected to the gate of the ancillary IGFET so as to bias same to the potential of the input and output terminals in the quiescent state in which the voltage divider is not traversed by any current.

We claim: 
     
       1. A circuit arrangement for converting bipolar incoming signals of widely varying amplitudes into amplitude-limited binary outgoing signals, comprising   a processing stage with two branches, a first branch including a first IGFET and a second branch including a second IGFET connected in cascade across a direct-current supply, said first IGFET having a source connected to one supply terminal, said second IGFET having a gate and a drain connected to the other supply terminal, a drain of said first IGFET and a source of said second IGFET being jointly connected to an output terminal supplied with said outgoing signals;   an input terminal coupled to a generator of said incoming signals;   a voltage divider inserted between said input terminal and said output terminal having a mean voltage intermediate the potentials of said supply terminals, said first IGFET having a gate connected to a tap of said voltage divider for establishing a predetermined reference potential on said output terminal in a quiescent state;   a protective diode inserted between said input terminal and said one supply terminal so as to be reverse-biased in said quiescent state and to break down in the presence of an abnormally high incoming signal of a certain polarity; and   an ancillary IGFET with a source connected to said input terminal, a drain connected to said other supply terminal and a gate connected to a point of biasing potential maintaining said ancillary IGFET nonconductive except in the presence of an incoming signal of the opposite polarity approaching a forward-conduction threshold of said protective diode, the conductivity of said ancillary IGFET upon such approach being sufficient to prevent said threshold from being reached, wherein said biasing potential substantially equals said reference potential.   
     
     
       2. A circuit arrangement for converting bipolar incoming signals of widely varying amplitudes into amplitude-limited binary outgoing signals, comprising:   a processing stage with two branches, the first branch including a first IGFET and a second branch including a second IGFET connected in cascade across a direct-current supply, said first IGFET having a source connected to one supply terminal, said second IGFET having a gate and a drain connected to the other supply terminal, a drain of said first IGFET and a source of said second IGFET being jointly connected to an output terminal supplied with said outgoing signals, wherein said processing stage further includes a third and a fourth IGFET connected in cascade across said direct-current supply, said third IGFET having a source connected to said one supply terminal, said fourth IGFET having a gate and a drain connected to said other supply terminal, a gate and a drain of said third IGFET forming said junction with a source of said fourth IGFET, said gate and said drain of said third IGFET being connected to a voltage divider, said gate and said drain of said third IGFET being further connected with a gate of an ancillary IGFET, said third and fourth IGFETS being substantial duplicates of said first and second IGFETS, respectively, whereby said junction and said input and output terminals are maintained at substantially identical potentials in said quiescent state;   an input terminal coupled to a generator of said incoming signals;   said voltage divider inserted between said input terminal and said output terminal having a mean voltage intermediate the potentials of said supply terminals, said first IGFET having a gate connected to a tap of said voltage divider for establishing a predetermined reference potential on said output terminal in a quiescent stage;   a protective diode inserted between said input terminal and said one supply terminal so as to be reverse-biased in said quiescent state and to break down in the presence of an abnormally high incoming signal of a certain polarity; and   said ancillary IGFET with a source connected to said input terminal, a drain connected to said other supply terminal and a gate connected to a point of biasing potential maintaining said ancillary IGFET nonconductive except in the presence of an incoming signal of the opposite polarity approaching a forward-conduction threshold of said protective diode, the conductivity of said ancillary IGFET upon such approach being sufficient to prevent said threshold from being reached.   
     
     
       3. A circuit arrangement of converting bipolar incoming signals of widely varying amplitudes into amplitude-limited binary outgoing signals, comprising:   a processing stage with two branches, a first branch including a first IGFET and a second branch including a second IGFET connected in cascade across a direct-current supply, said first IGFET having a source connected to one supply terminal, said second IGFET having a gate and a drain connected to the other supply terminal, a drain of said first IGFET and a source of said second IGFET being jointly connected to an output terminal supplied with said outgoing signals, wherein said processing stage further includes a third and a fourth IGFET connected in cascade across said direct-current supply, said third IGFET having a source connected to said one supply terminal, said fourth IGFET having a gate and a drain connected to said other supply terminal, a gate and a drain of said third IGFET forming said junction with a source of said fourth IGFET, said gate and said drain of said third IGFET being connected to a voltage divider, said gate and said drain of said IGFET being further connected with a gate of an ancillary IGFET, said third and fourth IGFETS being substantial duplicates of said first and second IGFETS, respectively, whereby said junction and said input and output terminals are maintained at substantially identical potentials in said quiescent state;   an input terminal coupled to a generator of said incoming signals;   said voltage divider inserted between said input terminal and said output terminal having a mean voltage intermediate the potentials of said supply terminals, said first IGFET having a gate connected to a tap of said voltage divider for establishing a predetermined reference potential on said output terminal in a quiescent state;   a protective diode inserted between said input terminal and said one supply terminal so as to be reverse-biased in said quiescent state and to break down in the presence of an abnormally high incoming signal of a certain polarity; and   said ancillary IGFET with a source connected to said input terminal, a drain connected to said other supply terminal and a gate connected to a point of biasing potential maintaining said ancillary IGFET nonconductive except in the presence of an incoming signal of the opposite polarity approaching a forward-conduction threshold of said protective diode, the conductivity of said ancillary IGFET upon such approach being sufficient to prevent said threshold from being reached, said first, second, third and fourth IGFETS, said voltage divider, said protective diode and said ancillary IGFET are part of an integrated circuit with a substrate connected to said one supply terminal.   
     
     
       4. A circuit arrangement as defined in claim 1 wherein said first and second IGFETS, said voltage divider, said protective diode and said ancillary IGFET are part of an integrated circuit with a substrate connected to said one supply terminal. 
     
     
       5. A circuit arrangement for converting bipolar incoming signals of widely varying amplitude into amplitude-limited bipolar outgoing signals, comprising: a processing stage including a main IGFET connected in series with a load across a direct-current supply, said main IGFET having a source connected to one supply terminal and a drain connected to an output terminal;   an input terminal coupled to a generator of said incoming signals;   a voltage divider inserted between said input and output terminals, said main IGFET having a gate connected to a tap of said voltage divider for establishing a predetermined reference potential on said output terminal in a quiescent state;   a protective diode inserted between said input terminal and said one supply terminal, so as to be reverse-biased in said quiescent state and to break down in the presence of an abnormally high incoming signal of a certain polarity; and   an ancillary IGFET with a source connected to said input terminal, a drain connected to said other supply terminal and a gate connected to a point of biasing potential substantially equal to said reference potential.   
     
     
       6. A circuit arrangement as defined in claim 5, wherein said load comprises another IGFET with a drain electrode connected to said other supply terminal, a source electrode connected to said output terminal and a gate connected to one of said drain and source electrodes. 
     
     
       7. A circuit arrangement as defined in claim 5 wherein said main IGFET, said load, said voltage divider, said protective diode and said ancillary IGFET are part of an integrated circuit with a substrate connected to said one supply terminal. 
     
     
       8. A circuit arrangement for converting bipolar incoming signals of widely varying amplitude into amplitude-limited bipolar outgoing signals, comprising: a processing stage including a first main IGFET connected in series with a first load across a direct-current supply, said first main IGFET having a source connected to one supply terminal and a drain connected to an output terminal;   said processing stage further including a second main IGFET connected in series with a second load across said direct-current supply, said second main IGFET having a source connected to said one supply terminal;   an input terminal coupled to a generator of said incoming signals;   a voltage divider inserted between said input terminal and a junction between said second load and a drain of said second main IGFET, said second main IGFET having a gate connected to a tap of said voltage divider for establishing a predetermined reference potential on said junction in a quiescent state, said second main IGFET and said second load being substantial duplicates of said first main IGFET and said first load, respectively, whereby said junction and said input and output terminals are maintained at substantially identical potentials in said quiescent state;   a protective diode inserted between said input terminal and said one supply terminal, so as to be reverse-biased in said quiescent state and to break down in the presence of an abnormally high incoming signal of a certain polarity; and   an ancillary IGFET with a source connected to said input terminal, a drain connected to said other supply terminal and a gate connected to a point of biasing potential substantially equal to said reference potential.   
     
     
       9. A circuit arrangement as defined in claim 8, wherein said first load comprises a first IGFET with a drain electrode connected to said other supply terminal, a source electrode connected to said output terminal and a gate electrode to one of said electrodes; and wherein said second load comprises a second IGFET with a drain electrode connected to said other supply terminal, a source electrode connected to said junction and a gate electrode connected to one of said drain and source electrodes of said second IGFET. 
     
     
       10. A circuit arrangment as defined in claim 8, wherein said first and second main IGFET, said first and second loads, said voltage divider, said protective diode and said ancillary IGFET are part of an integrated circuit with a substrate connected to said one supply terminal.